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Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay.

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Presentation on theme: "Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay."— Presentation transcript:

1 Microprocessor Design Multi-cycle Datapath Nia S. Bradley Vijay

2 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

3 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

4 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

5 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

6 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

7 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

8 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

9 Fall 2010, Sep 15... ELEC 5200-001/6200-001 Lecture 5 9 Control FSM Instr. decode/reg. fetch/branch addr. ALU operation Write PC on branch condition Write memory data Write jump addr. to PC Write register Read memory data Instr. fetch/ adv. PC Compute memory addr. Write register lw or sw lw sw R B J Start State 0 1 23 45 6 7 8 9

10 Datapath PC Instr. reg. (IR) Mem. Data (MDR) ALUOut Reg. A Reg. B Reg. ALU Register file Addr. Data 4 Sign extend Shift left 2 0-5 0-15 16-20 21-25 IorD MemtoReg=0 ALUSrcB=00 ALUSrcA=1 RegDst=0 IRWrite RegWrite MemWrite MemRead in1 in2 out control MUX Shift left 2 0-25 28-31 PCSource PCWrite etc. 26-31 to Control FSM Memory “funct. code” 11-15 CC3 CC4

11 Problems & Concerns During simulation processor goes into a loop when fetching a new instruction During simulation processor goes into a loop when fetching a new instruction

12 Next Steps Implementation on FPGA board Implementation on FPGA board

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