1. Lecture 10: Computer Design Basics: The ALU and the Shifter Soon Tee Teoh CS 147

2. The ALU The Arithmetic/Logic Unit Performs both arithmetic and logic operations The Arithmetic Circuit needs to support the following instructions: Move AG = A IncrementG = A + 1 AddG = A + B SubtractG = A + B’ + 1 DecrementG = A - 1 from table 10-8, pg. 454from table 10-1, pg. 435

3. The Arithmetic Circuit B input logic B S0S0 S1S1 n n n A C in n X Y n-bit parallel adder G Function table of B input logic S 1 S 0 Y 0 0 all 0 0 1 B 1 0 B’ 1 1 all 1 Desired operation Inputs S 1 S 0 C in G = A + B 0 1 0 G = A + 1 0 0 1 G = A + B 0 1 0 G = A + B’ + 1 1 0 1 G = A – 1 1 1 0

4. The Logic Unit Needs to support the following instructions: ANDG = A ^ B ORG = A v B Exclusive ORG = A + B NOTG = A’ from table 10-8, pg. 454from fig 10-8, pg. 437 A B G S0S0 S1S1 4-to-1 MUX

5. Putting Arithmetic and Logic Together 4-bit G Select becomes [ S 2 S 1 S 0 C in ] 2-to-1 MUX One Stage of Logic Circuit One Stage of Arithmetic Circuit C in A B S 0 S 1 ABS0S1ABS0S1 0101 S G C in A B S 0 S 1 S2S2 C out to next bit

6. R0 n n R1 n n R2 n n R3 n n Load enable decoder 0 1 2 3 load MUX 01230123 01230123 MUX B 0101 Constant Arithmetic/Logic Unit Shifter B Select A Select MB Select A B H Select G Select MUX F 0101 MUX D 0101 Data from Memory MF Select MD Select 10 00 0010 0 0 Destination Select 01

7. Need to determine input signals Operation MF Select G Select H Select F = A 0 0000 XX F = A+1 0 0001 XX F = A+B 0 0010 XX F = A+B+1 0 0011 XX F = A+B’ 0 0100 XX F = A+B’+1 0 0101 XX F = A-1 0 0110 XX F = A 0 0111 XX F = A ^ B 0 1X00 XX F = A v B 0 1X01 XX F = A + B 0 1X10 XX F = A’ 0 1X11 XX F = B 1 XXXX 00 F = sr B 1 XXXX 01 F = sl B 1 XXXX 10 From Table 10-4, page 443

8. Timing Suppose that the propagation delay for each of the components is as follows –4-1 MUX: 5 ns –2-1 MUX: 3 ns –AND gate: 1 ns –Register: 4 ns –2-4 Decoder: 4 ns –ALU: 15 ns –Shifter: 7 ns Suppose that the set-up time of the registers is 2ns, and the hold time of the registers is 1 ns. What is the minimum clock period possible for this machine? What is the maximum clock frequency this machine can achieve? (Note: Clock frequency = Number of clock cycles per second)

9. Barrel Shifter Example: 4-bit barrel shifter, can shift input by 0, 1, 2 or 3 bits. S 0 S 1 determines how many bits to shift (left). Use 4 4-to-1 multiplexers. 4-bit Barrel Shifter 4 D 4 Y S1S1 S0S0 D1D0D3D2D1D0D3D2 Y1Y1 S1S1 S0S0 D3D2D1D0D3D2D1D0 Y3Y3 S1S1 S0S0 D0D3D2D1D0D3D2D1 Y0Y0 S1S1 S0S0 D2D1D0D3D2D1D0D3 Y2Y2 S1S1 S0S0 01230123 01230123 01230123 01230123 From Figure 10-9, page 441

10. Barrel Shifter 32-bit barrel shifter: can use 32 32-to-1multiplexers However, large fan-in undesirable. So, use layers of multiplexers Y0Y0 D0D2D0D2 D1D3D1D3 D2D0D2D0 D3D1D3D1 Y1Y1 Y2Y2 Y3Y3 0101 0101 0101 0101 0101 0101 0101 0101 S1S1 S0S0 Example: Use 2 layers of 4 2-to-1 multiplexers for 4-bit barrel shifter