1. Henry Hexmoor

2. 10-1 Computer Specification
Instruction Set Architecture (ISA) - the specification of a computer's appearance to a programmer at its lowest level
Computer Architecture - a high-level description of the hardware implementing the computer derived from the ISA
The architecture usually includes additional specifications such as speed, cost, and reliability.
Henry Hexmoor

3. Introduction (continued)
Simple computer architecture decomposed into:
Datapath for performing operations
Control unit for controlling datapath operations
A datapath is specified by:
A set of registers
The microoperations performed on the data stored in the registers
A control interface
Henry Hexmoor

4. Datapaths 10-2 Guiding principles for basic datapaths:
The set of registers
Collection of individual registers
A set of registers with common access resources called a register file
A combination of the above
Microoperation implementation
One or more shared resources for implementing microoperations
Buses - shared transfer paths
Arithmetic-Logic Unit (ALU) - shared resource for implementing arithmetic and logic microoperations
Shifter - shared resource for implementing shift microoperations
Henry Hexmoor

5. Datapath Example Figure 10-1
Four parallel-load registers (R0-R3)
Two mux-based register selectors
Register destination decoder
Mux B for external constant input
Buses A and B with external address and data outputs
ALU and Shifter with Mux F for output select
Mux D for external data input
Logic for generating status bits V, C, N, Z
Load enable
A select
B select
Write
A address
B address
D data n
Load R0 2 2 n n
Load R1 n 1
MUX 2 n 3 1
Load
MUX R2 2 3 n n
Load R3 n n 1 2 3 n
Register file
Decoder
D address
A data
B data 2
Constant in n n
Destination select n 1
MB select
MUX B
Bus A n
Address n
Out
Bus B
Data A B n
Out
G select
H select 4 A B 2 B S
|| C S V
2:0 in
Arithmetic/logic I R
Shifter I L C
unit (ALU) G H N n n Z
Zero Detect
MF select 1
MUX F
Function unit F n n
Data In
Henry Hexmoor
MD select 1
MUX D n
Bus D

6. Datapath Example: Performing a Microoperation
MD select 1
MUX D V C N Z n 2
A data
B data
Register file
MUX B
Address
Out
Data
Bus A
Bus B
Function unit A B
G select 4
Zero Detect
MF select F
MUX F
H select S
2:0
|| C in
Arithmetic/logic
unit (ALU) G
Shifter H
MUX 3
Decoder
Load
Load enable
Write
D data
D address
Destination select
Constant in
MB select
A select
A address
B select
B address R3 R2 R1 R0
Bus D
Data In I L R
Microoperation: R0 ← R1 + R2
Apply 1 to Load Enable to force the Load input to R0 to 1 so that R0 is loaded on the clock pulse (not shown)
The overall microoperation requires 1 clock cycle
Apply 0 to MF select and 0 to MD select to place the value of G onto BUS D
Apply 01 to A select to place contents of R1 onto Bus A
Apply 00 to Destination select to enable the Load input to R0
Apply 10 to B select to place contents of R2 onto B data and apply 0 to MB select to place B data on Bus B
Apply 0010 to G select to perform addition G = Bus A + Bus B
Henry Hexmoor

7. Arithmetic Logic Unit (ALU)
In this and the next section, we deal with detailed design of typical ALUs and shifters
Decompose the ALU into:
An arithmetic circuit
A logic circuit
A selector to pick between the two circuits
Arithmetic circuit design
Decompose the arithmetic circuit into:
An n-bit parallel adder
A block of logic that selects four choices for the B input to the adder
See next slide for diagram
Henry Hexmoor

8. Arithmetic Circuit Design Figure 10-3 and Table 10-1 and table 10-2 (pages 435, 438)
There are only four functions of B to select as Y in G = A + Y:
All 0’s B
All 1’s
Cin = 0
Cin = 1
G = A
G = A + 1
G = A + B
G = A + B + 1
G = A + B
G = A + B + 1
Subtraction
G = A – 1
G = A C in n A X n
n-bit n
G = X Y + Cin B
parallel
adder n
B input Y S
logic S 1
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out

9. Logic Circuit AND OR XOR NOT 0 0 0 1 1 1 1 0 1
The text gives a circuit implemented using a multiplexer plus gates implementing: AND, OR, XOR and NOT
Here we custom design a circuit for bit Gi by beginning with a truth table organized as logic operation K-map and assigning (S1, S0) codes to AND, OR, etc.
Gi = S0 Ai Bi + S1 Ai Bi S0 Ai Bi + S1 S0 Ai
Gate input count for MUX solution > 29
Gate input count for above circuit < 20
Custom design better
S1S0
AND OR
XOR
NOT
AiBi
0 0
0 1
1 1
1 0 1
Henry Hexmoor

10. Arithmetic Logic Unit (ALU)
The custom circuit has interchanged the (S1,S0) codes for XOR and NOT compared to the MUX circuit. To preserve compatibility with the text, we use the MUX solution.
Next, use the arithmetic circuit, the logic circuit, and a 2-way multiplexer to form the ALU. See the next slide for the bit slice diagram.
The input connections to the arithmetic circuit and logic circuit have been been assigned to prepare for seamless addition of the shifter, keeping the selection codes for the combined ALU and the shifter at 4 bits:
Carry-in Ci and Carry-out Ci+1 go between bits
Ai and Bi are connected to both units
A new signal S2 performs the arithmetic/logic selection
The select signal entering the LSB of the arithmetic circuit, Cin, is connected to the least significant selection input for the logic circuit, S0.
Henry Hexmoor

11. Arithmetic Logic Unit (ALU) Figure 10-7
The next most significant select signals, S0 for the arithmetic circuit and S1 for the logic circuit, are wired together, completing the two select signals for the logic circuit.
The remaining S1 completes the three select signals for the arithmetic circuit. C i + 1
One stage of
arithmetic
circuit
logic circuit
2-to-1
MUX S A B 2 G in
Henry Hexmoor

12. Combinational Shifter Parameters 10-4
Direction: Left, Right
Number of positions with examples:
Single bit:
1 position
0 and 1 positions
Multiple bit:
1 to n – 1 positions
0 to n – 1 positions
Filling of vacant positions
Many options depending on instruction set
Here, will provide input lines or zero fill
Henry Hexmoor

13. 4-Bit Basic Left/Right Shifter (Figure 10-8)3 I R L S
Serial
output L
output R 2 1 H M U X
Serial Inputs:
IR for right shift
IL for left shift
Serial Outputs
R for right shift (Same as MSB input)
L for left shift (Same as LSB input)
Shift Functions: (S1, S0) = 00 Pass B unchanged Right shift Left shift Unused
Henry Hexmoor

14. Barrel Shifter (Figure 10-9)D 3 S 1 M U X 2 Y
A rotate is a shift in which the bits shifted out are inserted into the positions vacated
The circuit rotates its contents left from 0 to 3 positions depending on S: S = 00 position unchanged S = 10 rotate left by 2 positions S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
See Table 10-3 in text for details (page 440)
Henry Hexmoor

15. Barrel Shifter (continued)
Large barrel shifters can be constructed by using:
Layers of multiplexers - Example 64-bit:
Layer 1 shifts by 0, 16, 32, 48
Layer 2 shifts by 0, 4, 8, 12
Layer 3 shifts by 0, 1, 2, 3
See example in section 12-2 of the text
2 dimensional array circuits designed at the electronic level
Henry Hexmoor

16. Datapath Representation 10-5
Here we move up one level in the hierarchy from that datapath
The registers, and the multiplexer, decoder, and enable hardware for accessing them become a register file
A register file is an array of fast registers
The ALU, shifter, Mux F and status hardware become a function unit
The remaining muxes and buses which handle data transfers are at the new level of the hierarchy
Address out
Data out
Constant in
MB select
Bus A
Bus B FS V C N Z
MD select n
D data
Write
D address
A address
B address
A data
B data 2 m x
Register file A B
Function
unit F 4
MUX B 1
MUX D
Data in
Henry Hexmoor

17. Datapath Representation (continued)
Address out
Data out
Constant in
MB select
Bus A
Bus B FS V C N Z
MD select n
D data
Write
D address
A address
B address
A data
B data 2 m x
Register file A B
Function
unit F 4
MUX B 1
MUX D
Data in
In the register file:
Multiplexer select inputs become A address and B address
Decoder input becomes D address
Multiplexer outputs become A data and B data
Input data to the registers becomes D data
Load enable becomes write
The register file now appears like a memory based on clocked flip-flops (the clock is not shown)
The function unit labeling is quite straightforward except for FS
Henry Hexmoor

18. Definition of Function Unit Select (FS) Codes (Table 10-4, page 443))H
Select,
and MF
in T of FS
Codes
FS(3:0) MF
Select G
Select(3:0) H
Micr
ooperation
0000 XX
0001
0010
0011
0100
0101
0110
0111
1000 1 X 00
1001 01
1010 10
1011 11
1100
XXXX
1101
1110
F A
F A + B - F A
A B Ù Ú sr sl Å
Boolean
Equations:
MF = F3 F2
Gi = Fi
Hi = Fi
Henry Hexmoor

19. The Control Word The datapath has many control inputs
The signals driving these inputs can be defined and organized into a control word
To execute a microinstruction, we apply control word values for a clock cycle. For most microoperations, the positive edge of the clock cycle is needed to perform the register load
The datapath control word format and the field definitions are shown on the next slide
Henry Hexmoor

20. The Control Word Fields
DA – D Address (destination)
AA – A Address
BA – B Address (source for MUXB
MB – Mux B (constant/source
FS – Function Select
MD – Mux D
RW – Register Write
The connections to datapath are shown in the next slide
Control word D A AA BA M B FS R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Henry Hexmoor

21. Control Word Block Diagram (Figure 10-11)8 14 13 11
Bus D
Constant in n
MUX B 1
D data
Write
D address
A address
B address
A data
B data x
Register file A B
Function
unit
MUX D
Data in
Bus A
Bus B R W 12 AA 15 D BA 9
Address out
Data out V C N Z 7 MD MB 6 4 FS 5 3 2
Henry Hexmoor

22. Control Word Encoding Table 10-5
Encoding of Control W D A ,
AA, B A MB FS MD R W
Function
Code
Function
Code
Function
Code
Function
Code
Function
Code R
000
Register F A
0000
Function
No write R 1
001
Constant 1
F A + 1
0001
Data In 1
Write 1 R 2
010
F A + B
0010 R 3
011
F A + B + 1
0011 R 4
100
F A + B
0100 R 5
101
F A + B + 1
0101 R 6
110
F A - 1
0110 R 7
111
F A
0111
F A Ù B
1000
F A Ú B
1001
F A Å B
1010 F
1011 A
F B
1100 F sr B
1101 F sl B
1110
Henry Hexmoor

23. Microoperations for the Datapath - Symbolic Representation Table 10-6W R 1 R 2 – R 3 R 1 R 2 R 3 R e g
ister
F A =
+ + B 1 F
unction
Write R 4 s
l R6 R 4 — R 6 R e g
ister F = sl B F
unction
Write R 7 R
7 1 + R 7 R 7 — Re
gister
F A = + 1
Function
Write R 1 R
0 2 + R 1 R —
Con s
tant
F A = + B
Func
tio n
Write
Data out R 3 —— R 3 R eg i s t e r — — N
o Wr it e R 4 D
ata in R 4 —— — —
Data in
Write R R 5 R R R e g
ister
F A = Å B F
unction
Write
Henry Hexmoor

24. Microoperations for the Datapath - Binary Representation Table 10-7
Microoperations from T a
Binary C o o
Results of simulation of the above on the next slide
Micr o- o p
eratio n D A B M F S R W 1
011
010 10 XX X
110
111 11
XXX
000 00
001
101 2 3 – 4 s
l R6 7
7 1 +
0 2
Data out
ata in
Henry Hexmoor

25. Datapath Simulation Figure 10-124 7 5 2 3 6 X 14 10 18
255 12 8
clock DA AA BA
Constant_in MB
Address_out
Data_out FS
Status_bits
Data_in MD RW
reg0
reg1
reg2
reg3
reg4
reg5
reg6
reg7
Henry Hexmoor

26. Instruction Set Architecture (ISA) for Simple Computer (SC) 10-7
A programmable system uses a sequence of instructions to control its operation
An typical instruction specifies:
Operation to be performed
Operands to use, and
Where to place the result, or
Which instruction to execute next
Instructions are stored in RAM or ROM as a program
The addresses for instructions in a computer are provided by a program counter (PC) that can
Count up
Load a new address based on an instruction and, optionally, status information
Henry Hexmoor

27. Instruction Set Architecture (ISA) (continued)
The PC and associated control logic are part of the Control Unit
Executing an instruction - activating the necessary sequence of operations specified by the instruction
Execution is controlled by the control unit and performed:
In the datapath
In the control unit
In external hardware such as memory or input/output
Henry Hexmoor

28. ISA: Storage Resources Figure 10-13
The storage resources are "visible" to the programmer at the lowest software level (typically, machine or assembly language)
Storage resources for the SC =>
Separate instruction and data memories imply "Harvard architecture"
Done to permit use of single clock cycle per instruction implementation
Due to use of "cache" in modern computer architectures, is a fairly realistic model
Program counter
(PC)
Instruction
memory 2 15 x 16
Register file x 8 16
Data
memory 2 15 x 16
Henry Hexmoor

29. ISA: Instruction Format
A instruction consists of a bit vector
The fields of an instruction are subvectors representing specific functions and having specific binary codes defined
The format of an instruction defines the subvectors and their function
An ISA usually contains multiple formats
The SC ISA contains the three formats presented on the next slide
Henry Hexmoor

30. ISA: Instruction Format Figure 10-14
(c) Jump and Branch
(a) Register
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
ister B (SB) 15 9 8 6 5 3 2
(b) Immediate
Operand (OP)
Address (AD)
(Right)
(Left)
The three formats are: Register, Immediate, and Jump and Branch
All formats contain an Opcode field in bits 9 through 15.
The Opcode specifies the operation to be performed
More details on each format are provided on the next three slides
Henry Hexmoor

31. ISA: Instruction Format (continued)
(a) Register
Opcode
Destination
register (DR)
Source reg-
ister A (SA)
ister B (SB) 15 9 8 6 5 3 2
This format supports instructions represented by:
R1 ← R2 + R3
R1 ← sl R2
There are three 3-bit register fields:
DR - specifies destination register (R1 in the examples)
SA - specifies the A source register (R2 in the first example)
SB - specifies the B source register (R3 in the first example and R2 in the second example)
Henry Hexmoor

32. ISA: Instruction Format (continued)
(b) Immediate
Opcode
Destination
register (DR)
Source reg-
ister A (SA) 15 9 8 6 5 3 2
Operand (OP)
This format supports instructions described by:
R1 ← R2 + 3
The B Source Register field is replaced by an Operand field OP which specifies a constant.
The Operand:
3-bit constant
Values from 0 to 7
The constant:
Zero-fill (on the left of) the Operand to form 16-bit constant
16-bit representation for values 0 through 7
Henry Hexmoor

33. ISA: Instruction Format (continued)
(c) Jump and Branch
Opcode
Source reg-
ister A (SA) 15 9 8 6 5 3 2
Address (AD)
(Right)
(Left)
This instruction supports changes in the sequence of instruction execution by adding an extended, 6-bit, signed 2s-complement address offset to the PC value
The 6-bit Address (AD) field replaces the DR and SB fields
Example: Suppose that a jump is specified by the Opcode and the PC contains 45 (0… ) and Address contains – 12 (110100). Then the new PC value will be: 0… (1…110100) = 0… (45 + (– 12) = 33)
The SA field is retained to permit jumps and branches on N or Z based on the contents of Source register A
Henry Hexmoor

34. ISA: Instruction Specifications
The specifications provide:
The name of the instruction
The instruction's opcode
A shorthand name for the opcode called a mnemonic
A specification for the instruction format
A register transfer description of the instruction, and
A listing of the status bits that are meaningful during an instruction's execution (not used in the architectures defined in this chapter)
Henry Hexmoor

35. ISA: Instruction Specifications (continued)
fications for the Simple
Comput
er - Part 1
Instr u
ctio O pc
ode
Mnem on ic
Form a t D
escrip
tion St s
Bits
Move A MO V A RD
,RA R
[DR]
R[SA ] N , Z
Increment
INC RA
R[DR] [
SA]
+ 1
Add
ADD
RA,RB
+ R[
SB]
Subtr ct
SUB - e
crement
DEC 1
AND Ù
R[SB
, Z OR
,RA,RB Ú
Exclusive OR
XOR Å
R[SB] NO T N,
Henry Hexmoor

36. ISA: Instruction Specifications (continued)
fications for the Simple
Comput
er - Part 2
Instr u
ctio O pc
ode
Mnem on ic
Form a t D
escrip
tion St s
Bits
Move B MO VB RD
,RB R
[DR]
R[SB]
Shift Right
SHR , RB
R[DR] sr
Shift Left
SHL sl
Load Imm e
diate
LDI P
zf OP
Add Immediate
ADI
RA,OP
R[SA]
+ zf OP
Load LD
,RA M[ SA ]
Store ST
RA,RB M
[SA]
Branch
Zero
BRZ
A,AD
if (R[ S
A] =
0) PC PC
+ s A
Negative
BRN
A] < J mp
JMP C
R[SA
Henry Hexmoor

37. ISA:Example Instructions and Data in Memory
Memory Repr
esentation
of Instruc t
ions and
Data D
eciimal Ad d r
ess
Mem o y C
ontents
Dec i
mal Op
cod e
Other F
elds
eration 25
00001
01 001
010
011
5 (Subtract)
DR:1,
SA:2,
SB:3 R1 R2 - R3 35
01000
00 000
100
101
32 (Store ) S
A:4, SB:5 M[
R4] R5 45
10000
10 010
111
66 (Add Im
mediate)
DR: 2
, S A : 7
, OP :3 R R7
+ 3 55
11000
00 101
110
96 (Branch on Z ro
AD:
44, SA:6
If R6 = 0, PC 20 70
000
00000
Data = 1
92. Aft
r execution of
instruction in
35, 8 .
Henry Hexmoor

38. Single-Cycle Hardwired Control 10-8
Based on the ISA defined, design a computer architecture to support the ISA
The architecture is to fetch and execute each instruction in a single clock cycle
The datapath from Figure will be used
The control unit will be defined as a part of the design
The block diagram is shown on the next slide
Henry Hexmoor

39. Figure 10-15 IR(8:6) || IR(2:0) Extend V C Branch PC N Control Z P J B
Address L B C
Instruction
memory RW D
Instruction DA
Register
file AA A B BA
Zero fill
IR(2:0)
Constant in
Instruction decoder 1 MB
MUX B
Address out
Bus A
Bus B
Data out MW D B A M F M R M P J B A A A B S D W W L B C A B
Data in
Address FS
CONTROL V
Data
Function C
memory
unit
Figure 10-15 N
Data out Z F
Data in 1 MD
MUX D
Henry Hexmoor
Bus D
DATAPATH

40. The Control Unit
The Data Memory has been attached to the Address Out and Data Out and Data In lines of the Datapath.
The MW input to the Data Memory is the Memory Write signal from the Control Unit.
For convenience, the Instruction Memory, which is not usually a part of the Control Unit is shown within it.
The Instruction Memory address input is provided by the PC and its instruction output feeds the Instruction Decoder.
Zero-filled IR(2:0) becomes Constant In
Extended IR(8:6) || IR(2:0) and Bus A are address inputs to the PC.
The PC is controlled by Branch Control logic
Henry Hexmoor

41. PC Function (continued)
Branch Control determines the PC transfers based on five of its inputs defined as follows:
N,Z – negative and zero status bits
PL – load enable for the PC
JB – Jump/Branch select: If JB = 1, Jump, else Branch
BC – Branch Condition select: If BC = 1, branch for N = 1, else branch for Z = 1.
The above is summarize by the following table:
PC Operation PL JB BC
Count Up X
Jump 1
Branch on Negative (else Count Up)
Branch on Zero (else Count Up)
Henry Hexmoor

42. Instruction Decoder
The combinational instruction decoder converts the instruction into the signals necessary to control all parts of the computer during the single cycle execution
The input is the 16-bit Instruction
The outputs are control signals:
Register file addresses DA, AA, and BA,
Function Unit Select FS
Multiplexer Select Controls MB and MD,
Register file and Data Memory Write Controls RW and MW, and
PC Controls PL, JB, and BC
The register file outputs are simply pass-through signals: DA = DR, AA = SA, and BA = SB Determination of the remaining signals is more complex.
Henry Hexmoor

43. Instruction Decoder (continued)
The remaining control signals do not depend on the addresses, so must be a function of IR(13:9)
Formulation requires examining relationships between the outputs and the opcodes…
Observe that for other than branches and jumps, FS = IR(12:9)
This implies that the other control signals should depend as much as possible on IR(15:13) (which actually were assigned with decoding in mind!)
To make some sense of this, we divide instructions into types as shown in the table on the next page
Henry Hexmoor

44. Instruction Decoder (continued)
ruth a
ble for Instruction Decoder Logic
Instruction Function
ype
Instruction Bits
Contr ol W o r d
Bits 15 14 13 9 M B D R P L J C
Function unit operations using
registers X
X X
Memory read 1
Memory write
register and constant
Conditional branch on zero (Z) X
Conditional branch on negative (N)
X X
Unconditional J
ump
X X
Henry Hexmoor

45. Instruction Decoder (continued)
The types are based on the blocks controlled and the seven signals to be generated; types can be divided into two groups:
Datapath and Memory Control (First 4 types)
PC Control (Last 3 types)
In Datapath and Memory Control blocks controlled are considered:
Mux B (1st and 4th types)
Memory and Mux D (2nd and 3rd types)
By assigning codes with no or only one 1 for these, implementation of MB, MD, RW and MW are simplified.
In Control Unit more of a bit setting approach was used:
Bit 15 = Bit 14 = 1 were assigned to generate PL
Bit 13 values were assigned to generate JB.
Bit 9 was use as BC which contradicts FS = 0000 needed for branches. To force FS(6) to 0 for branches, Bit 9 into FS(6) is disabled by PL.
Also, useful bit correlations between values in the two groups were exploited in assigning the codes.
Henry Hexmoor

46. Instruction Decoder (continued)
The end result by use of the types, careful assignment of codes, and use of don't cares, yields very simple logic:
This completes the design of most of the essential parts of the single-cycle simple computer 19 – 17 DA 16 14 AA 13 11 BA 10 MB 9 6 FS 5 MD 4 RW 3 MW 2 PL 1 JB BC
Instruction
Opcode DR SA SB
Control word 15 12 8
Henry Hexmoor