1. EE 5340 Semiconductor Device Theory Lecture 23 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2. Project Discussion – Ideal Diode equations ©rlc L23-14Apr20112 Ideal diode, J s expd(V a /(  V t )) –ideality factor,  Recombination, J s,rec exp(V a /(2  V t )) –appears in parallel with ideal term High-level injection, (J s *J KF ) 1/2 exp(V a /(2  V t )) –SPICE model by modulating ideal J s term V a = V ext - J*A*R s = V ext - I diode *R s

3. Project Discussion – Ideal Diode Forward Current Equations ©rlc L23-14Apr20113 Id = area·(Ifwd - Irev) Ifwd = forward current = Inrm·Kinj + Irec·Kgen Inrm = normal current = IS·(eVd/(N·Vt)-1) if: IKF > 0 then: Kinj = (IKF/(IKF+Inrm)) 1/2 else: Kinj = 1 Irec = recombination current = ISR·(eVd/(NR·Vt)-1)

4. ©rlc L23-14Apr20114 Dinj –N~1, rd~N*Vt/iD –rd*Cd = TT = –Cdepl given by CJO, VJ and M Drec –N~2, rd~N*Vt/iD –rd*Cd = ? –Cdepl =? SPICE Diode Model 

5. Derivation Tips ©rlc L23-14Apr20115

6. 6

7. 7 Ideal 2-terminal MOS capacitor/diode x -x ox 0 SiO 2 silicon substrate V gate V sub conducting gate, area = LW t sub 0 y L

8. ©rlc L23-14Apr20118 Band models (approx. scale) EoEo EcEc EvEv q  ox ~ 0.95 eV metalsilicon dioxidep-type s/c q  m = 4.1 eV for Al EoEo E Fm E Fp EoEo EcEc EvEv E Fi q  s,p q  Si = 4.05eV E g,ox ~ 8 eV

9. ©rlc L23-14Apr20119 Flat band condition (approx. scale) E c,Ox EvEv AlSiO 2 p-Si q(  m -  ox )= 3.15 eV E Fm E Fp EcEc EvEv E Fi q(  ox -  Si )=3.1eV E g,ox ~8eV q  fp = 3.95eV

10. ©rlc L23-14Apr201110 Equivalent circuit for Flat-Band Surface effect analogous to the extr Debye length = L D,extr = [  V t /(qN a )] 1/2 Debye cap, C’ D,extr =  Si /L D,extr Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ D,extr

11. ©rlc L23-14Apr201111 Accumulation for V gate < V FB SiO 2 p-type Si V gate < V FB V sub = 0 E Ox,x <0 x -x ox 0 t su b holes

12. ©rlc L23-14Apr201112 Accumulation p-Si, V gs < V FB Fig 10.4a*

13. ©rlc L23-14Apr201113 Equivalent circuit for accumulation Accum depth analogous to the accum Debye length = L D,acc = [  V t /(qp s )] 1/2 Accum cap, C’ acc =  Si /L D,acc Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ acc

14. ©rlc L23-14Apr201114 Depletion for p-Si, V gate > V FB SiO 2 p-type Si V gate > V FB V sub = 0 E Ox,x > 0 x -x ox 0 t su b Acceptors Depl Reg

15. ©rlc L23-14Apr201115 Depletion for p-Si, V gate > V FB Fig 10.4b*

16. ©rlc L23-14Apr201116 References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986