1. HIGH-PERFORMANCE LONGEST PREFIX MATCH LOGIC SUPPORTING FAST UPDATES FOR IP FORWARDING DEVICES Author: Arun Kumar S P Publisher/Conf.: 2009 IEEE International Advance Computing Conference (IACC 2009) Speaker: Han-Jhen Guo Date: 2009.04.22 1

2. OUTLINE Introduction The Proposed Scheme Performance 2

3. INTRODUCTION - MOTIVATION BGP Prefix updates. Data collected from AS65000 3 an increased update activity during 2007-2008 an increased update activity during 2007-2008

4. INTRODUCTION - TYPICAL TCAM How a typical TCAM is used for LPM 4 table would need a pre-computation if update

5. I NTRODUCTION - M AIN C ONTRIBUTIONS OF T HIS P APER Propose a novel architecture for performing LPM using associative memory architecture Eliminate the need for pre-computation on the IP prefixes before populating the routing table priority encoder logic of TCAM's Substitute the priority encoder logic of TCAM's with Longest Prefix Finder (LPF) logic allows faster updates to the table without compromising the lookup speed advantage of the TCAM based methods 5

6. THE PROPOSED SCHEME - OVERALL ARCHITECTURE Overall Architecture 6 des IP Prefix Entry Unit Longest Prefix Finder Longest Prefix Finder (external lookup for nexthop)

7. THE PROPOSED SCHEME - OVERALL ARCHITECTURE (eg.) 7

8. The Proposed Scheme - Implement & Hardware Design Prefix Entry Unit (PEU) address value ( addr ) along with its associated mask ( pfx ) match found flag ( mf ) enables the LPF logic to do a comparison of only prefixes mf = ( key AND pfx ) XNOR ( key AND addr ) 8

9. THE PROPOSED SCHEME - IMPLEMENT & HARDWARE DESIGN Longest Prefix Finder (LPF) Comparison of the prefixes is performed only on matched prefixes ( mf = 1) Parallel bit-wise manner From the Least Significant Bit (LSB) towards the Most Significant Bit (MSB) 9

10. THE PROPOSED SCHEME - IMPLEMENT & HARDWARE DESIGN Longest Prefix Finder (LPF) Prefix Bit Logic Block (PBLB) pfx d(i, j) ： jth bit of ith pfx mfpfx en( i, j ) ： mf of ith pfx f(i) ： feedback input; indicates whether any of the PBLB's in its bit-slice is a logic 1 lbr(i, j) ： generate the f(i) and the mi(i, j) 10

11. THE PROPOSED SCHEME - IMPLEMENT & HARDWARE DESIGN Longest Prefix Finder (LPF) Overall architecture 11

12. THE PROPOSED SCHEME - IMPLEMENT & HARDWARE DESIGN (eg.) 12

13. THE PROPOSED SCHEME - IMPLEMENT & HARDWARE DESIGN Update Use a stack maintained by the software for identifying the free locations Insertion Write the value to the address provided by a stack pop O(1) Deletion require the address of the deleted entry to be pushed into the stack O(1) 13

14. PERFORMANCE Average prefix size (from a core router from AS 65000 ) 14 get a hit by traversing about 10 bit-slices in the LPF circuit get a hit by traversing about 10 bit-slices in the LPF circuit

15. PERFORMANCE Performance Comparison 15

16. PERFORMANCE Storage requirements for 1500 entries similar storage requirements as that of a TCAM less than the other methods considerably 16

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