1. An On-Chip IP Address Lookup Algorithm Author: Xuehong Sun and Yiqiang Q. Zhao Publisher: IEEE TRANSACTIONS ON COMPUTERS, 2005 Presenter: Yu Hao, Tseng Date: 2013/03/06

2. Outline Introduction A Hardware Design Reference Model Convert Longest Prefix Match to Range Search Problem Put The Tree in Memory Experimental Study Conclusion

3. Introduction Nowadays, one access to on-chip memory takes 1-5ns for SRAM and about 10ns for DRAM. Compression algorithm for storing IP address lookup table Compress the keys in a tree node Use a shared pointer in a tree node Use a bottom-up process from the leaf to the root scheme to build the tree

4. A Hardware Design Reference Model

5. Convert Longest Prefix Match to Range Search Problem

6. Convert Longest Prefix Match to Range Search Problem (Cont.)

7. Put The Tree in Memory Compressed Endpoints Common leading bits (Red region) Common trailing zeros (Green region) Shared Pointers

8. Put The Tree in Memory (Cont.) Example 144 bits in each memory row Internal node or leaf bits 1 bit Number of keys 4 bits Number of skip bits IPv4 : 5 bits IPv6 : 7 bits Number of trailing zeros IPv4 : 5 bits IPv6 : 7 bits Keys IPv4 : 144 – 1 – 4 – 5 – 5 – 20 = 109 bits IPv6 : 144 – 1 – 4 – 7 – 7 – 20 = 105 bits Next tree pointer 20bits

9. Put The Tree in Memory (Cont.)

10. Build the Tree from the Bottom up Variant One Let { e 1, e 2, e 3, …, e n } be the set of endpoints. Assume that { e 1, e 2, e 3, e 4 } are stored in the first leaf node, then the endpoint {e 5 } will be stored in the next higher level node. Assume that { e 6, e 7, e 8, e 9, e 10 } are stored in the second leaf node, then the endpoint {e 11 } will be stored in the next higher level node. {e 1 } and {e 5 } are involved to find the the common leading bits of the first leaf node. { e 1, e 2, e 3, e 4 } are used to find the common trailing zeros of the first leaf node. {e 5 } and {e 11 } are involved to find the common leading bits of the second leaf node. { e 6, e 7, e 8, e 9, e 10 } are used to find the common trailing zeros of the second leaf node.

11. Put The Tree in Memory (Cont.) First leaf node common leading bits 10000 common trailing zeros 00000000 Second leaf node common leading bits 1 common trailing zeros 00000000

12. Put The Tree in Memory (Cont.) Build the Tree from the Bottom up Variant Two Let { e 1, e 2, e 3, …, e n } be the set of endpoints. Assume that { e 1, e 2, e 3, e 4 } are stored in the first leaf node, { e 5, e 6, e 7, e 8, e 9 } are stored in the second leaf node, and { e 10, e 11, e 12, e 13 } are stored in the third leaf node and so on. Let n 1 be the number of common leading bits of {e 4 } and {e 5 }. Let n 2 be the number of common leading bits of { e 5, e 6, e 7, e 8, e 9 }. Let n 3 = max {n 1 + 1, n 2 }. Truncate the n 3 most significant bits of e 5 and padded with trailing zeros to form a 32 bit endpoint, e 2 ’.

13. Put The Tree in Memory (Cont.) Build the Tree from the Bottom up Variant Three Variant One + Variant Two Variant Four Divide the endpoints into groups according to their leading bits

14. Put The Tree in Memory (Cont.) Optimization The level one (root) doesn’t need the next tree pointer field. put the root in the registers the skip bits field For example, if we skip 2 bits in the first level and 7 bits in the second level, we only need to store 7- 2 = 5 as additional bits to skip. From the experiments, 3 bits is enough for IPv4.

15. Experimental Study Port Merge

16. Experimental Study (Cont.) Comparisons on Variants

17. Experimental Study (Cont.) Results Using Real-Life Tables

18. Experimental Study (Cont.) Results Using the Expanded IPv4 Tables

19. Experimental Study (Cont.) Results Using the Expanded IPv6 Tables

20. Conclusion We developed a novel algorithm which is tailored to hardware technology. The distinguishing merit of our algorithm is that it has a very small memory requirement.