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DCal A Custom Integrated Circuit for Calorimetry at the International Linear Collider.

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Presentation on theme: "DCal A Custom Integrated Circuit for Calorimetry at the International Linear Collider."— Presentation transcript:

1 DCal A Custom Integrated Circuit for Calorimetry at the International Linear Collider

2 2 October 25, 2005IEEE NSS 2005 – Puerto Rico Authors Jim Hoff 1 – Fermilab Abder Mekkaoui – Fermilab Ray Yarema – Fermilab Gary Drake – Argonne National Lab Jose Repond – Argonne National Lab [1] Presenter/contact – jimhoff@fnal.gov

3 3 October 25, 2005IEEE NSS 2005 – Puerto Rico Out with the old… Traditional calorimeters are based on sandwich design, alternating layers of Active medium (detector) and Absorber (to incite shower development) Total energy is summed in a tower and measured as accurately as possible with a broad dynamic range (16 or 18 bits) What is the resolution requirements for a smaller tower? How small does the calorimeter “tower” have to be to require only one bit of dynamic range? What else could you do with such a device?

4 4 October 25, 2005IEEE NSS 2005 – Puerto Rico In with the new… With extremely fine segmentation (~1cm 2 ), the calorimeter becomes digital Individual shower identification becomes possible Total shower energy is a simple summation of the hit segments within a shower Particle Flow Algorithms The idea… ECAL HCAL γ π+π+ KLKL Charged particles Tracker measured with the Neutral particles Calorimeter

5 5 October 25, 2005IEEE NSS 2005 – Puerto Rico In with the new… [1]Linear Collider Detector R&D, May 12, 2004, http://www.hep.anl.gov/repond/DOE_ Review_LCD_May_2004.ppt http://www.hep.anl.gov/repond/DOE_ Review_LCD_May_2004.ppt [2] Calorimetry at the Linear Collider, November 12, 2004, http://www.hep.anl.gov/repond/Calori metry_IIT_Nov_2004.ppt http://www.hep.anl.gov/repond/Calori metry_IIT_Nov_2004.ppt [3] “Electronics for LC DHCAL”, CALICE Meeting, March 4, 2005, http://www.hep.anl.gov/repond/05031 4_drake.ppt http://www.hep.anl.gov/repond/05031 4_drake.ppt Particle Flow Algorithms The idea… ECAL HCAL γ π+π+ KLKL Charged particles Tracker measured with the Neutral particles Calorimeter

6 6 October 25, 2005IEEE NSS 2005 – Puerto Rico Anatomy of a PFA-based calorimeter DCal – A Custom ASIC to service this array 400,000 channels in a 1 cubic meter test structure destined for the Fermilab testbeam.

7 7 October 25, 2005IEEE NSS 2005 – Puerto Rico DCal Requirements Service 64 channels of segmented Calorimeter. Function adequately for two leading PFA calorimeter technologies – RPCs and GEMs. The PFA needs a digital “snapshot” of the state of the calorimeter, so the chip must receive signals and amplify, discriminate as “hits”, tag with a time stamp (24 bits) for reconstruction, notify downstream electronics of event. Capable of responding to a trigger OR generating its own. Use/Do Not Use an internal delay FIFO. Fully programmable, no exotic external biases. Relatively quiet. Minimal pads; serialize everything. Readout Architecture CANNOT limit system performance

8 8 October 25, 2005IEEE NSS 2005 – Puerto Rico DCal Flow Diagram

9 9 October 25, 2005IEEE NSS 2005 – Puerto Rico Analog Front End Identical to the FSSR2 front end See, “FSSR2, a Self-Triggered Low Noise Readout Chip for Silicon Strip Detectors” Re, Valerio, et al, NSS 2005, Oct. 25, 2005. The two gains allow this chip to be used with RPC- based calorimeters (high-signal, slow) and with GEM-based calorimeters (low-signal, fast).

10 10 October 25, 2005IEEE NSS 2005 – Puerto Rico Catching Hits The chip must be programmable to Accept or Reject Hits. The chip must catch all hits no matter how short the duration. The chip must catch each hit once and only once no matter how long the duration. The chip must gather all hits from within one full time slice. The chip must be available to receive the next hit as soon as possible. Latched Hit

11 11 October 25, 2005IEEE NSS 2005 – Puerto Rico Trigger Control The system requirements call for either an internal or external trigger to be issued on data that is either directly caught or has been delayed by 20 clock periods. The fifoFull signal gates a trigger request such that it will only activate if there is room in the FIFO. Triggers are valid across the positive edge of the clock.

12 12 October 25, 2005IEEE NSS 2005 – Puerto Rico Programming Interface SPI-like Interface 3-wires: Shift In, Shift Out, Shift Control Chip address embedded in command Allows bussed lines Wildcard chip address Default chip address Externally identical to the FPIX/FSSR programming interface but with about 1/2 the number of transistors. Set, Reset registers Send registers to a hardwired default value Write to, read from registers

13 13 October 25, 2005IEEE NSS 2005 – Puerto Rico Data Output 1 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 T 1 T 0 Sync Bit Data Data Type 00=SYNC 01=DATA 10=TIME 11=STATUS Data output is in the form of a single-bit serial stream packed into 11-bit words. Data is valid whenever the Clk Out changes state. Sync words and status words have single word frames. Data frames are 11 words wide (121 bits).

14 14 October 25, 2005IEEE NSS 2005 – Puerto Rico Simulations – System Performance Successfully evacuated 2000 events with no errors at an aggregate hit frequency of >420kHz. Much faster than necessary. Limiting factor to performance is the FIFO depth System architecture (in particular the FIFO) is scalable, so even higher hit frequencies are easily possible.

15 15 October 25, 2005IEEE NSS 2005 – Puerto Rico Results Fabricated in 0.25um CMOS by TSMC. Bench tests verified full functionality Awaiting system test with both RPC and GEM detectors

16 16 October 25, 2005IEEE NSS 2005 – Puerto Rico Results Fabricated in 0.25um CMOS by TSMC. Bench tests verified full functionality Awaiting system test with both RPC and GEM detectors Programming Interface Pipeline FIFO Front Ends 1-32 Front Ends 33-64 Serializer

17 Background Slides

18 18 October 25, 2005IEEE NSS 2005 – Puerto Rico Motivation – ILC Requirements The type of physics we want to see coming out of the ILC requires an extremely high Jet Energy Resolution from the Calorimeters (30%/√E jet ). 60%/√E 30%/√E Separation of WW and ZZ by J.C. Brient

19 19 October 25, 2005IEEE NSS 2005 – Puerto Rico Out with the old… Most colliding beam calorimeters are based on sandwich design, alternating layers of Active medium (detector) and Absorber (to incite shower development) Calorimeter measures photons and hadrons in jets Typically with different response: e/h ≠ 1 Leads to poor jet energy resolution of > 100%/√E The ZEUS Calorimeter was tuned Scintillator and Uranium thickness to achieve e/h ~ 1 Best single hadron energy resolution ever 35%/√E 50%/√E Jet Energy Resolution

20 20 October 25, 2005IEEE NSS 2005 – Puerto Rico In with the new… Need a very good tracker in a high magnetic field Need a calorimeter with extremely fine segmentation (~1cm 2 ) Particle Flow Algorithms The idea… ECAL HCAL γ π+π+ KLKL Charged particles Tracker measured with the Neutral particles Calorimeter

21 21 October 25, 2005IEEE NSS 2005 – Puerto Rico Engineering perspective on PFAs A Tradeoff : Wide dynamic range in a comparatively small number of channels (traditional) versus low dynamic range on a vast number of channels (PFA). More in common with pixel and silicon strip tracking designs than with traditional calorimeter designs. (Lots and lots of channels.) Pure digital as soon as possible. (Many storage solutions.) Single, broadly applied threshold voltage. Achievable speeds – especially for the analog front ends.

22 22 October 25, 2005IEEE NSS 2005 – Puerto Rico Background – RPC vs GEM

23 23 October 25, 2005IEEE NSS 2005 – Puerto Rico Programming Interface Register Name AddressDefault PLSR DataThe magnitude of the (internal) pulse 00001 2 (1)00000000 2 (0) IntDBasic Integrator Bias (IntVbn1)00010 2 (2)10001011 2 (139) Shp2DShaper bias (ShpVbp2)00011 2 (3)01111001 2 (121) Shp1DShaper bias (ShpVbp1)00100 2 (4)01110100 2 (116) BlrDBaseline restorer bias (BlrVbp1)00101 2 (5)01010000 2 (81) VtnDDifferential Threshold Voltage n- side (see p. 2) 00110 2 (6)00000000 2 (0) VtpDDifferential Threshold Voltage p- side (see p. 2) 00111 2 (7)11111111 2 (255) DCRDigital Control Register01000 2 (8)00000000 2 (0) InjInject Register (see p. 2)01001 2 (9)N/A KillKill or Mask Register (see p. 2)01011 2 (11)N/A SCRSmart Core Reset11011 2 (27)N/A STRSmart Time Reset11110 2 (30)N/A

24 24 October 25, 2005IEEE NSS 2005 – Puerto Rico Data Output 1 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 T 1 T 0 Sync Bit Data Data Type 00=SYNC 01=DATA 10=TIME 11=STATUS 1T 23 T 22 T 21 T 20 T 19 T 18 T 17 T 16 10 1T 15 T 14 T 13 T 12 T 11 T 10 T 09 T 08 10 1T 07 T 06 T 05 T 04 T 03 T 02 T 01 T 00 10 1D 63 D 62 D 61 D 60 D 59 D 58 D 57 D 56 01 1D 55 D 54 D 53 D 52 D 51 D 50 D 49 D 48 01 1D 47 D 46 D 45 D 44 D 43 D 42 D 41 D 40 01 1D 39 D 38 D 37 D 36 D 35 D 34 D 33 D 32 01 1D 31 D 30 D 29 D 28 D 27 D 26 D 25 D 24 01 1D 23 D 22 D 21 D 20 D 19 D 18 D 17 D 16 01 1D 15 D 14 D 13 D 12 D 11 D 10 D 09 D 08 01 1D 07 D 06 D 05 D 04 D 03 D 02 D 01 D 00 01


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