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1 m 3 Prototype Digital Hadron Calorimeter Collaborators Argonne National Laboratory Boston University University of Chicago Fermilab University of Texas.

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Presentation on theme: "1 m 3 Prototype Digital Hadron Calorimeter Collaborators Argonne National Laboratory Boston University University of Chicago Fermilab University of Texas."— Presentation transcript:

1 1 m 3 Prototype Digital Hadron Calorimeter Collaborators Argonne National Laboratory Boston University University of Chicago Fermilab University of Texas at Arlington

2 New Concept of Digital Hadron Calorimeter Small number (~10 5 ) of readout channels Large number (~10 8 ) of readout channels Large number (10 – 18) of bits per channel ECAL: large number of bits per channel HCAL: small number (1 – 2) of bits per channel Traditional calorimeter Excellent single particle resolution Digital hadron calorimeter Reduces ‘confusion’ term Preserves single particle (hadrons) resolutions

3 Development of the Readout Electronics 40 layers à 1 m 2 Real challenge 400,000 readout channels Cheap (≤ 1$/channel) 1 cm 2 readout pads Low cross-talk, noise… Conceptual design of system I Front-end ASIC II Data concentrator III VME data collection IV Trigger and timing system

4 Front-end ASIC ASIC performance specified in 41 page document 64 inputs with choice of input gains RPCs (streamer and avalanche), GEMs… Triggerless or triggered operation 100 ns clock cycle Output: hit pattern and time stamp

5 ASIC design work at FNAL Abderrezak Mekkaoui James Hoff FNAL Ray Yarema First design meeting between ANL and FNAL in February Design work started in June First submission hopefully in CY2004 Pictures of chip layout and data structure by James Hoff

6 Analog circuitry taken from recently built FSSR chip (BTeV) Only one gain setting Modifications not before CY2005 Hit catcher with possibility to mask noisy channels Chip has data indicator essentially a fast OR 32 Inputs Digital IO

7 Timestamp resets every 1 second unique value for clock speed of 10 MHz Pipeline to accommodate trigger decision can be removed in triggerless operation Write out buffer

8 Sync Word Status Word S7S7 S6S6 S5S5 S4S4 S3S3 S2S2 S1S1 S0S0 111 Time Word T7T7 T6T6 T5T5 T4T4 T3T3 T2T2 T1T1 T0T0 101 Data Word D7D7 D6D6 D5D5 D4D4 D3D3 D2D2 D1D1 D0D0 011 Bit Zero Output word structure

9 S7S7 S6S6 S5S5 S4S4 S3S3 S2S2 S1S1 S0S0 111 S7S7 Accept/Reject All Hits S6S6 Triggered/Data Push S5S5 Sync Pulse S4S4 Enable Pipeline/Disable Pipeline S3S3 Not Used S2S2 Time Stamp Bit 2 S1S1 Time Stamp Bit 1 S0S0 Time Stamp Bit 0 The Status Word

10 Sync WordStatus Word Sync WordStatus Word 1 Time Slice 1 Time Slice 1 Time Slice 1 Time Slice Ordinary Data I/O Operation

11 Sync WordData Frame Sync WordStatus Word 1 Time Slice 12 Time Slices 1 Time Slice 1 Time Slice When a TimeSlice is triggered

12 1Time WordTime Stamp (7:0) 2Time WordTime Stamp (15:8) 3Time WordTime Stamp (23:16) 4Data WordHits(7:0) 5Data WordHits(15:8) 6Data WordHits(23:16) 7Data WordHits(31:24) 8Data WordHits(39:32) 9Data WordHits(47:40) 10Data WordHits(55:48) 11Data WordHits(63:56) The Data Frame 11 bits x 11 words

13 ASIC Development Concept Realization Verilog SchematicLayout Digital Simulations SPICE Simulations Port Lay-out Simulations

14 Schematic LayoutVerification Standard Cell Library Hit Catchers Chip Has Data Pipeline FSSR Channels FIFO Time Stamp Clock control Data IO Programming interface Drivers Status of Design Effort As of July 25, 2004 Goal: first submission in October, 2004

15 SimulationCompletion Verilog Model Development (from Discriminator Output to Pads) Verilog Simulation using Monte Carlo Data High Data Rate simulation Verilog Model versus Schematic Comparison Simulation/Functional Verification

16 Time scales R&D with chambers Essentially completed Electronic readout system Design and prototype ASIC Specify entire readout system Prototype subcomponents Construction of m 3 Prototype Section Build chambers Fabricate electronics Tests in particle beams Without and with ECAL in front


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