1. Chapter 3 - Digital Logic Level Gates Basic Digital Logic Memory –Storage Hierarchy CPU –PII –PicoJava Bus –PCI Homework: –Chapter 3 # 1, 4, 6, 12, 25, 35, 37, 40 (Due 4/22)

2. Gates and Boolean Algebra X = !A;

3. Functions _ _ _ M=ABC+ABC+ABC+ABC M =(!A) && B && C || A &&(!B)&& C || A && B &&(!C) || A && B && C

4. Completeness of NAND and NOR

5. Equivalence and Minimization XX+YY = X+Y

6. Identities for formula transform

7. Transforming formulas

8. 0-60 in 4.2 sec.

9. Memory SR Latch

10. Clocked latches Clocked SR latch Clocked D latch

11. Clocking

12. D Flip-Flop

13. 4 x 3 (3?)

14. Simple Bus

15. Dynamic RAM

16. CPU chip I

17. Buses Everywhere!

18. Bus overview P IV (.013 micron) –36 addr lines –64 data lines –MANY control lines

19. Synchronous bus overview

20. Bus arbitration

21. P II cpu bus 33 ADDR 64 Data Bus pipeline –Arbitration –Request –Error –Snoop –Response –Data

22. PicoJava Built-in ram/PROM bus Built-in PCI bus support 16 Built-in I/O lines

23. A real bus - PCI

24. PCI - more