1. Optimality FPGA Technology Mapping: A Study of Optimality Andrew C. Ling M.A.Sc. Candidate University of Toronto Deshanand P. Singh Ph.D. Altera Corporation Professor Stephen D. Brown Altera Corporation Toronto University of Toronto

2. Goals Determine how “good” current FPGA LUT based technology mappers are in terms of area-optimality Determine how “good” current FPGA LUT based technology mappers are in terms of area-optimality A. Farrahi and M. Sarrafzadeh (1994). Area problem shown to be NP-Hard A. Farrahi and M. Sarrafzadeh (1994). Area problem shown to be NP-Hard

3. Method Take a set of benchmark circuits and technology map them to LUTs using one of the best existing LUT based technology mappers. Take a set of benchmark circuits and technology map them to LUTs using one of the best existing LUT based technology mappers. Devise a resynthesis technique that is able to remove LUTs from these pre-existing technology mapped circuit. Devise a resynthesis technique that is able to remove LUTs from these pre-existing technology mapped circuit. The more LUTs that can be removed, the farther the original technology mapping was from the area-optimal solution. The more LUTs that can be removed, the farther the original technology mapping was from the area-optimal solution.

4. Resynthesis Attempt to map a cone with X LUTs to another cone with less than X LUTs Attempt to map a cone with X LUTs to another cone with less than X LUTs

5. Sliding Window Approach Resynthesize subcircuits Resynthesize subcircuits Does not give the globally optimal solution; however gives an indication of the area “left on the table” Does not give the globally optimal solution; however gives an indication of the area “left on the table”

6.   Defined over a set of variables, V Background: The Propositional Satisfiability (SAT) problem Given a formula, f : C1C1 C2C2 C3C3 a=b=c=1 (a,b,c) (C 1,C 2,C 3 )   Comprised of a conjunction of clauses   Each clause is a disjunction of literals of the variables V Example : SAT: Seek an assignment of to the variables, V, which sets expression to ‘1’.

7. Construction of CNF T. Larrabee, “Test pattern generation using Boolean satisfiability," TCAD, 1992 (Plaisted's and Greenbaum's encoding which is based on Tseitin's work) Creates a Characteristic Function for circuits x1x2x1x2x1x2x1x2gf0001 0101 1001 1100 0010 0110 1010 1111 f=(x 2 +¬g) (x 1 +¬g) (¬x 2 +¬x 1 +g)

8. Construction of CNF (cont’d) f AND = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) f OR = (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) f OR f total = f AND f OR (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g)

9. Formulating Resynthesis Problem 2-LUT fg ? Can function f be implemented in circuit g ? Can function f be implemented in circuit g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g Does there exist a configuration to g such that for all inputs to g, f is equivalent to g

10. Formulating Resynthesis Problem 2-LUT fg ? Derive characteristic function H for circuit g Derive characteristic function H for circuit g Replace all instances of g in H with f Replace all instances of g in H with f –H[g/f] (g ≡ f ) –f is equivalent to g

11. Formulating Resynthesis Problem 2-LUT fg ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? (g ≡ f ) (g ≡ f )

12. Formulating Resynthesis Problem 2-LUT fg ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? Does there exist a configuration to g such that for all inputs to g, f is equivalent to g ? l 1 …l m x 1 …x n (g ≡ f ) AE

13. Formulating Resynthesis Problem 2-LUT fg SAT Express as a QBF with inputs ( x 1 …x n ) and configuration bits ( l 1 …l m ) Express as a QBF with inputs ( x 1 …x n ) and configuration bits ( l 1 …l m ) l 1 …l m x 1 …x n (g ≡ f ) l 1 …l m x 1 …x n (g ≡ f ) Remove quantifiers to form a SAT problem (A. Biere. “Resolve and Expand”, SAT’04) Remove quantifiers to form a SAT problem (A. Biere. “Resolve and Expand”, SAT’04) AE

14. Resynthesis Structures Used Given a MFFC with 7 or less inputs and containing more than 2 LUTs, map it to: Given a MFFC with 7 or less inputs and containing more than 2 LUTs, map it to: Given a MFFC with 10 or less inputs and containing more than 3 LUTs, map it to: Given a MFFC with 10 or less inputs and containing more than 3 LUTs, map it to: 4-LUT

15. Resynthesis Results, 4-LUTs

16. Digital Logic Blocks with Tricks How intelligent are current technology mappers when it comes to some common digital logic blocks? How intelligent are current technology mappers when it comes to some common digital logic blocks?

17. Techmap 4:1 MUX with 4-LUTs 00 01 10 11

18. Techmap 4:1 MUX with 4-LUTs 00 01 10 11

19. Techmap 4:1 MUX with 4-LUTs 00 01 10 11

20. Resuts using 4-LUTs

21. Conclusions Current 4-LUT technology mappers still have room for improvement (~5% on average, up to 10% for some circuits) Current 4-LUT technology mappers still have room for improvement (~5% on average, up to 10% for some circuits) For some logic blocks, current technology mappers have a very difficult time finding the optimal mapping to 4-LUTs (~36% geomean, up to 67%). For some logic blocks, current technology mappers have a very difficult time finding the optimal mapping to 4-LUTs (~36% geomean, up to 67%). Still has difficultly particularly for non-disjoint decomposition. Still has difficultly particularly for non-disjoint decomposition.

22. Future Work Explore BDDs, QBF solvers and All Solution SAT solvers to speed up process Explore BDDs, QBF solvers and All Solution SAT solvers to speed up process –If fast enough, this technique can be used as a valid resynthesis technique. Use Multiple Output Resynthesis Use Multiple Output Resynthesis Search for other optimal configurations of common logic blocks, used in a caching scheme for resynthesis Search for other optimal configurations of common logic blocks, used in a caching scheme for resynthesis –After technology mapping, search for digital logic blocks found in our cache, replace digital logic block with the cached optimal configuration

23. Questions?