# Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical.

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Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu 1, Victor Shih 2, Rupak Majumdar 2 and Lei He 1 1 Electrical Engineering Dept., UCLA 2 Computer Science Dept., UCLA Presented by Victor Shih Address comments to lhe@ee.ucla.eduhttp://eda.ee.ucla.edu/publications.html

Outline Background and Motivation Review of Standard SAT-based Boolean Matching Proposed Improvements Experimental Results Conclusion and Future Work

Background FPGA technology mapping  Map a design into a network of Programmable Logic Blocks (PLBs)  Optimize for area, speed and/or power PLBs containing heterogeneous devices requires Boolean matching (BM) to determine whether function f can be implemented by hardware component H  3A.1 Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates [Hu, ICCAD’07]

Example: Boolean Matching (BM) for PLBs Answers a Yes-No question:  Can a Boolean function f be implemented in PLB p?  If yes, give the configuration bits for all LUTs. f 1 = e*a + c*a + d*a + b*a f 2 = a + b + c + d + e f 1 = (e + c + d + b)*a i.e., f 1 = z*a z = e + c + d + b z e c d b a f1f1 L0 (0000)0 L1 (0001)1 L2 (0010)1 ……… L15(1111)1

Motivation for SAT-Based PLB BM Application of FPGA PLB Boolean matching  Technology mapping  Re-synthesis Existing BM algorithms  Decomposition-based BM lacks flexibility, i.e., the algorithm is only applicable to selected BLE structure [Cong, TCAD’01]  BDD based BM is not scalable (memory explosion) [Ciric, TCAD’03]  Fast BM is hard to deal with programmable devices [Wei, ISQED’06]  Improvements over Ling’s algorithm obtain 3x speedup [Sean, DAC’06] and 10x speedup [Jason, FPGA’07] SAT-based BM [Ling, DAC’05][Safarpour, DAC’06][Cong, FPGA’07]  Introduces extreme flexibility  Provide a tradeoff between memory and runtime to deal with complicated BLE structures  Still slow, hard to be applied to complex PLBs

Review: SAT-Based Encoding for BM Encoding non-programmable devices:  Requires common/interconnect variables  Is a linear time procedure Example: f AND = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) f OR = (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g) f total = f AND f OR = (x 2 +¬z 1 ) (x 1 +¬z 1 ) (¬x 2 +¬x 1 + z 1 ) (¬x 3 +g) (¬z 1 +g) (x 3 +z 1 + ¬g)

Review: SAT-Based Encoding for BM Encoding programmable devices:  Configuration bits are encoded f LUT =( x 1 + x 2 + ¬L 0 + z 1 ) ( x 1 + x 2 + L 0 + ¬ z 1 ) ( x 1 + ¬ x 2 + ¬L 1 + z 1 ) ( x 1 + ¬ x 2 + L 1 + ¬ z 1 ) (¬ x 1 + x 2 + ¬L 2 + z 1 ) (¬ x 1 + x 2 + L 2 + ¬ z 1 ) (¬ x 1 + ¬ x 2 + ¬L 3 + z 1 ) (¬ x 1 + ¬ x 2 + L 3 + ¬ z 1 )

Review: SAT-Based Encoding for BM G LUT2 =( x 1 + x 2 + ¬L 0 + z) ( x 1 + x 2 + L 0 + ¬ z) ( x 1 + ¬ x 2 + ¬L 1 + z) ( x 1 + ¬ x 2 + L 1 + ¬ z) (¬ x 1 + x 2 + ¬L 2 + z) (¬ x 1 + x 2 + L 2 + ¬ z) (¬ x 1 + ¬ x 2 + ¬L 3 + z) (¬ x 1 + ¬ x 2 + L 3 + ¬ z) G AND2 = ( x 3 + ¬f ) (¬ x 3 + ¬f ) ( ¬x 3 + ¬z + f ) G = G AND2 · G LUT2 x1x2x3x1x2x3 f 0000 0010 0101 0110 1001 1011 1101 1111 SAT: G expand = G[X/000, f/0, z/z 0 ] · G[X/001, f/0, z/z 1 ] G[X/010, f/1, z/z 2 ] · G[X/011, f/0, z/z 3 ] G[X/100, f/1, z/z 4 ] · G[X/101, f/1, z/z 5 ] G[X/110, f/1, z/z 6 ] · G[X/111, f/1, z/z 7 ] Boolean function Configuration bits are encoded as SAT literals The solution of this SAT problem corresponds to the Boolean matching results

The Problem of Input Permutations [Ling, DAC’05] Virtual MUXes increase runtime exponentially! ? ? ?

Impact of Virtual MUXes

Outline Background and Motivation Review of Standard SAT-based Boolean Matching Proposed Improvements Experimental Results Conclusion and Future Work

Symmetries in Circuits and PLB Functional Symmetries  Variable a and variable b are symmetric if swapping a and b does not change the truth table of function F(…, a, …, b, …)  E.g.: F(a, b, c) = a·(b + c), where b and c are symmetric  General symmetries which consider the permutations of more than two variables can also be explored Architectural Symmetries  Structures of certain inputs of a PLB are equivalent  E.g.: Inputs of the primary input LUTs of PLBs are symmetric F(b, a, c, d)

Impact of Considering Symmetries The number of distinct permutations under symmetries decreases substantially  Functional symmetries and architecture symmetries independently reduce permutations by 100x

Overall Algorithm Boolean function Functional symmetry detection Prune via architecture symmetries Non-redundant Permutation Set (NPS) Is NPS empty? Pre-processing target PLB - one-time cost Target architecture Pre-calculate architecture symmetry patterns Architecture symmetry information Characteristic function template Generate characteristic function template Pop permutation p Exit Y N

Overall Algorithm (cont.) Replicate CNFs of p Solve SAT problem SAT? Return implementable Target architecture Pre-calculate architecture symmetry patterns Architecture symmetry information Characteristic function template Generate characteristic function template Pre-processing target PLB - one-time cost Exit Y Is NPS empty? Pop permutation p Y N N

Experimental Results Experimental conditions:  Tested with Boolean functions in MCNC circuits  Target PLB was “ PLB_d ”  Used “ miniSAT1.14 ” as SAT solver engine Obtained over 100x speedup compared to the standard approach [Ling ’05 ]  Additional 2x achieved using implicant table representation

Experimental Results Improvement makes SAT-based Boolean matching feasible in the context of technology mapping and re-synthesis

Other SAT Symmetry Detection Techniques Shatter/Saucy - general symmetry-breaking tool for SAT (version released Sept ‘07) [Aloul, Markov, Sakallah, DAC’03]  Augments SAT problem, adding symmetry breaking clauses  Same SAT engine used

Problems in the Proposed Algorithm (Following improvements yet to be published) Conjunctive normal form (CNF) clause generation dominates runtime  Generally CNF generation time to SAT solution time is an order of magnitude greater

Improvement - Iterative Clause Testing miniSAT’s incremental SAT reasoning suggests possible improvement:  If any subset of clauses is unsatisfiable, the entire set is unsatisfiable  Since SAT testing is relatively inexpensive, we can iteratively test larger and larger subsets to minimize CNF generation  Asymptotically, worst-case runtime is equivalent to non-incremental testing – overhead for additional iterations is insignificant  Experimentally, this resulted in roughly 3x speedup a + j + d !b + e + s t + a + !f e + !m + !p + !e + g + r + !e … 1 2 3 IterationsClauses …

Improvement – Template Clause-Set Approach miniSAT’s “assumptions” parameter suggests possible improvement:  Facilitates parameterization of SAT literals for later resolution  We can minimize clause generation time by formulating a set of clauses which is common to all permutations to test, and adding only the clauses specific to each permutation as assumptions  Experimentally, this resulted in roughly 10x speedup  Note that this approach precludes the iterative clause testing approach

x1x2x3x1x2x3 f' 000f1f1 001f5f5 010f3f3 011f7f7 100f2f2 101f6f6 110f4f4 111f8f8 Template Clause-Set Approach Detail Example:  Every permutation will have the same set of input values, but each will correspond to different outputs x1x2x3x1x2x3 f 000f1f1 001f2f2 010f3f3 011f4f4 100f5f5 101f6f6 110f7f7 111f8f8 x1x2x3x1x2x3 f' 000f1f1 100f2f2 010f3f3 110f4f4 001f5f5 101f6f6 011f7f7 111f8f8 f f' = f ( x 3, x 2, x 1 )f' P 1 = G expand ∙ ¬f 1 ∙ ¬ f 2 ∙ f 3 ∙ ¬ f 4 ∙ f 5 ∙ f 6 ∙ f 7 ∙ f 8 P 2 = G expand ∙ ¬ f 1 ∙ f 2 ∙ ¬ f 3 ∙ f 4 ∙ ¬ f 5 ∙ ¬ f 6 ∙ ¬ f 7 ∙ f 8 … SAT: G expand = G[X/000, f/f 1, z/z 0 ] · G[X/001, f/f 2, z/z 1 ] G[X/010, f/f 3, z/z 2 ] · G[X/011, f/f 4, z/z 3 ] G[X/100, f/f 5, z/z 4 ] · G[X/101, f/f 6, z/z 5 ] G[X/110, f/f 7, z/z 6 ] · G[X/111, f/f 8, z/z 7 ]

CNF Generation Runtime Breakdown Template clause-set implementation obtains average 10x speedup of CNF generation time

Conclusions and Future Work An improvement for SAT-based Boolean matching is presented by considering functional and architectural symmetries Over 100x speedup is obtained compared to the standard SAT-based Boolean matching approach Future Work  Integrate the improved SAT-based Boolean matcher into heterogeneous FPGA technology mapping phase  Perform architecture exploration using our improved technology mapper

Thanks Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping Yu Hu, Victor Shih, Rupak Majumdar and Lei He

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