1. Progress report of new PHENIX pilot chip Hiroyuki Kano (RIKEN) 1. Overview 2. Digital pilot ASIC and test board 3. Functionalities and test result 4. GOL test

2. 4x BUS Pilot Module Overview Pilot module (on-detector) Readout chip control signals 4x32bit@10M Hz data Optical data link DAQ (counting room) CLK Command Sensor Readout chip Digital pilot ASIC GOL

3. A A CLK Digital pilot G G ctrl data 32b data A. ALICE original busopt A A Digital pilot G G ctrl data Digital pilot G G ctrl Digital pilot G G ctrl data CLK Digital pilot G G ctrl data B. For PHENIX 4x bus bus G G ctrl data opt A A CLK G G ctrl data 2x32b C. PHENIX pilot w/ new chip 32b 1.6Gbps mode Why New Digital pilot ASIC? OE/EO 2x32b G = Gigabit Optical Link (GOL) G G Digital pilot New chip = Analog monitor chip G G A A

4. Digital pilot ASIC, Packaging, and Test board Bare-chips were delivered from CERN(IBM). [11 Oct.] Bare-chips ware packaged for the test purpose by Fujitsu. (QFP256, 23packages) [19 Oct.] ASIC test board with chip was delivered. [22 Nov.] 8mm 6mm QFP256 package 28mm Packaged ASICBare chipDigital pilot ASCI test board

5. PHENIX Pilot Chip Overview Serial control stream L1 L2y L2nrst JTAG(GOL) JTAG(RO) CE Shreg clev nevr strobe FO DATA_1 DATA_0 Feedback JTAG Readout- chip control Pixel data input (10MHz) pixel data output (40MHz) Pilot Chip has three main blocks 1. Multiplexer converts readout data; 4x32bit@10MHz to 1x32bit@40MHz. 2. Readout chip controller make readout sequence. 3. Command decoder decodes commands from serial stream. MUX 32bit bus width Readout chip Controller Command Decoder Probing Test pattern generating Test board Test setup for the new digital pilot ASIC

6. Command Decoder Command decoder Serial control stream Commands, JTAG, etc commandsCode binary reset_control_receiver00000000 reset_global11101000 reset_gol11100100 reset_pixel11100010 trst_pixel11100001 trse_standard_on10110100 trse_standard_off10110010 l101010110 l2y01011010 l2n01010101 testpulse11011000 jtag1010(TMS,~TMS,TDI,~TDI) idle11001100 GOL reset command by new chip [1-DEC-04] testpulse command by new chip [1-DEC-04] serial stream reset_gol testpulse serial stream out in Below 2 pictures shows you that command signal corresponding to serial stream is probed.

7. Readout chip Controller nevr_i ce_0 ce_1 ce_9 Readout sequence by new chip [1-DEC-04] This picture shows the readout sequence; The nevr_i and ce_n are generated from L1 and L2. Wave form of readout sequence (ALICE digital pilot document) Reference :http://a.home.cern.ch/a/akluge/www/work/ali ce/spd/spd_documents/ops2003book.pdfhttp://a.home.cern.ch/a/akluge/www/work/ali ce/spd/spd_documents/ops2003book.pdf

8. MUX CLK40 and output data by new chip [9-DEC- 04] This picture shows that the original data bus (BUS A31-0) and additional data bus (BUS B31-0) can be processed correctly. This test pattern is; BUS A31-0 pattern = up counter; 00000000,11111111,22222222,… BUS B31-0 pattern = down counter; FFFFFFFF,EEEEEEEE,DDDDDDDD,… ….. slot0slot1slot2slot3slot0slot1slot2slot3 Reference :http://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_documents/ops2003book.pdfhttp://a.home.cern.ch/a/akluge/www/work/alice/spd/spd_documents/ops2003book.pdf Probing Test pattern generating Test board

9. Summary of ASIC test Packaging and test board assembly are finished. Result of functionality test seems fine, but not completed yet. Functionality test will be finished in this month.

10. GOL test setup GOL test board: It can be mounted on Vertex2- pro board via PMC connector Vertex2-pro evaluation board: =Vertex2-pro interface board Vertex2-pro has integrated hi- speed deserializer. OE/EO converter: Agilent evaluation board GOL test full setup GOL Vertex2pro EO converter Optical fiver

11. FPGA program overview GOL test program is based on the xilinx evaluation source. Vertex2-pro generates test vector, serializes, and comparisons between generated vector and GOL output vector. generating test signal comparisonserialize (integrated) display (LED&LCD) deserializer (GOL) Vertex2-pro program

12. Test step 3Gbps→1.6Gbps (cupper wire) V2P RocketIO Vertex2pro TED Vertex2-pro test Board 1.6Gbps (optical fiver) V2P Agilent EO board Agilent OE board 1.6Gbps (optical fiver) V2P GOL test board Agilent OE board 1. 2. 3. 1.Cupper wire setup [26 Oct.] System test, Developing GB-ethernet protocol, Changing the link speed* 2.Optical fiver setup [12 Nov.] Optical component test 3.GOL test *Changing the link speed Vertex2-pro test board has 156MHz crystal for the V2-pro maximum speed. In our case, we need 1.6Gbps.

13. Summary of GOL test Test setup is ready now. Gigabit Ethernet protocol for GOL is developed.