1. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 1 - VIth Workshop on Front End Electronics Perugia, Mai 2006 M.Trimpl DEPFET – collaboration: MPI/MPE Munich L.Andricek, P.Lechner, H.G. Moser, R.H.Richter, L.Strüder, G.Lutz, J.Treis U Mannheim P.Fischer, F.Giesen, C.Kreidel, I.Peric U Bonn M.Koch, R.Kohrs, H.Krüger, P.Lodomez, L.Reuen, C.Sandow, M.Trimpl, E.v.Törne, J.J.Velthuis, N.Wermes U Prague Z.Doležal, P Kodyš, D.Scheirich U Aachen L.Feld, W. Karpinski, K.Klein DEPFET pixels for the ILC and associated readout electronics

2. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 2 - - Motivation: DEPFET pixels at the ILC - Sensor production and measurements - FE r/o-electronics (CURO): - architecture - input cascode - current memory cell - hit detection & zero suppression - Results: CURO II chip - ILC DEPFET-System (lab, beam test) - Summary and Outlook outline

3. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 3 - frame: ~300µm sensor: ~50µm layer one readout steering r=15 mm 8 modules ‘holes’ to reduce material thinned silicon sample vertexing at the ILC layer one close to beam pipe (15mm) readout in 50µs (layer one) triggerless operation (on chip hit identification and zero suppression) ~ 0.1 % X 0 / layer material budget low power (10W ?)  passive cooling some ILC requirements [L.Andricek, MPI Munich]

4. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 4 - DEPFET principle and clear operation  FET-Transistor integrated in pixel (first amplification)  charge generation in whole substrate (d=50µm, ENC=100e - : S/N > 40)  charge collection due to electric field  figure of merit: internal gain (g q =  I D /  q)  remove charge via „clear“ contact  remove all charge  complete clear no „reset-noise“, needed at the ILC clearprinciple

5. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 5 - sensor production for the ILC gate clear drain fabricated: matrices with up to 128x64 pixel, 450µm thick linear double pixel structures (22x36 µm 2 pixels) (high density layout) new production started recently 03/2006: matrices up to 512x512 pixel full ILC length column & row test structures special cleargate to support clear operation

6. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 6 - radiation tolerance: sensor 200krad shift of threshold voltage of MOSFETs (oxide thickness ~200nm) shift: - 4…- 6 V saturation after 200 kRad shaping-time = 6µs, @ RT single pixel spectrum from iron-peak: ENC ~ 15 e - (comparable with preirrad. structures) 55 Fe ~ 1MRad irradiation up to 1MRad using 60 Co [L.Andricek, MPI Munich]

7. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 7 - complete clear achieved with static clear gate! required voltages small (5 – 7 V) – important for future SWITCHER! clear (gate) operation does not decrease after irradiation (1MRad) (Clear off = 2V) Complete clear in only 10 ns: Measurements on mini matrix devices ‘noise’ becomes minimal if clearing is complete! U Clear-off = 3 V region of complete clear high-E clear efficiency various designs (high-E, no high-E) geometries (length of clear gate) operating conditions (static or clocked clear gate) static! [C.Sandow, Bonn]

8. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 8 - matrix operation I Drain = Pedestal + Signal I Drain I Drain = Pedestal I Drain = Pedestal + Signal low power consumption, low multiple scattering but line rate: ≥ 20MHz ideal r/o: current based, no I  U

9. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 9 - steering chip SWITCHER 4.6 mm 4.8 mm typical value: < 200  nmos (Vlow): PMOS GNDA Out VDDA/GNDA NMOS Vhigh Vlow >50% Layout size ! C row =15pF   = 3ns ( fast steering ! ) [I.Peric, Mannheim]

10. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 10 - regulated cascode keeps potential at input constant Hit-Finder finds up to 2 hits per cycle: - analog currents to outA, outB - digital hit position stored in HIT-RAM FIFOs digital part is scanned with HIT-Finder pedestal current is subtracted at input node after reset (fast CDS) pedestal + signal is stored in current memory cell overview: CURO-Architecture CUrrent ReadOut

11. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 11 - CURO II 128 input channel (DEPFET - Matrix) 12x 8bit DACs Biasing, test currents, thresholds pads (communication): fast signals: LVDS steering unit: ~ 20 steering signals TSMC 0.25µm 5 metal layer 4.5 x 4.5 mm 2 11/2003 analog part: current memory cells, comparator digital part: Hit-Finder, RAM, FIFO

12. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 12 - input cascode   C L. R in present-matrices : 7.5pF; final ILC-matrices:  40pF !! cascode compensates load capacitance control dynamic behavior (pole-zero cancellation) CUROIIb: power down feature IBias = 1µA static operation  fix input potential 500µA  high speed operation higher gm by higher IBias  speed vs. power

13. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 13 - I1I1 I2I2 I out= I 1 – I 2 I in I = I in + I B [Hughes/Toumazou] (use of cascode techniques !) current memory cell advantages: high dynamic range (with reduced supply voltage) precise current subtraction easy drivers not needed

14. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 14 - 1/g S C G C BUS I input (independent of R) noise contribution time response switch optimizes time response noise vs. bandwidth minimize bus capacitance g m small, C g large, C BUS minor importance noise vs. time response

15. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 15 - layout: two stage sampling cell 25 µm 40µm (+) improves linearity (non linearity due to charge injection) (-) more complex steering ! (all signals generated „on-chip“) calculated noise: ~ 25nA, bandwidth: 50MHz different designs: coarse stage: fast, noise does not contribute fine stage: „slower“, optimized for noise schematic: coarse sampling:

16. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 16 - Linearity + Pedestal Subtraction linearity: pedestal subtraction: transfer gain: 1.00± 0.01 INL= 2,3 % (Integral Non Linearity) e.g. 5µA (10%) pedestal dispersion  75nA after pedestal subtraction all analog measurements @ 24MHz line rate (sampling with 48MHz)

17. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 17 - Noise & Dispersion noise: Dispersion: DEPFET r/o with CURO: ENC ~ 90 e - (g q =500pA/e - )  ~ 35nA after calibration dispersion < noise

18. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 18 - fast hit-identification 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 Address = 2, 6, (3) parallel tree architecture finds up to 2 hits per clock cycle propagation delay: 2 log(#channels) = 7 only ! serial hit finding clock > 2 GHz needed „aggressive“ even with 0.09 µm ! Hit-Finder: out back up down down_back up_back leaf („lower“ part) [P.Fischer]

19. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 19 - Hit-Finder: Layout challenge: 128 leaves of the tree in linear layout 7 level  128 leaves 85µm 25 µm rad. tolerant design ! overall: 3200 x 85 µm 2

20. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 20 - works fine up to: 110MHz total power consumption: digital tests:  250W for whole vtx-d (continuous operation) bunch structure 1 :199  pulsed mode (1:30) ~ 10W CURO II measurements (cont‘d) Hitscanner HIT-RAM serial-out hit-address: rowstamp, column Input-FIFO alternating testpattern w_clk s_clk s_ptr w w_clk counter rowstamp 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 expected mean rate (1. layer): 1-2 hits @ 20MHz

21. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 21 - Current Readout CURO II Gate Switcher Clear Switcher DEPFET Matrix (450µm thick) 64x128 pixels, 36 x 28.5µm 2 ILC DEPFET-System USB 2.0 based digital interface board Analog board with ADCs, DAQ … Hybrid-PCB [H.Krüger, Bonn]

22. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 22 - 2 mm 3 mm ILC DEPFET-System in the lab irradiation with 55 Fe (6keV  1700 e - ) 75 µm thick Tungsten-Mask system performance: speed: line rate ~2 MHz noise: 220 e - (from noise peak) Integral-Non-Linearity = 0.75% for 8500e - 241 Am

23. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 23 - noise contributions: system Sensor (shot noise) 8e - (50µs), 45e - (current r/o) (1/f noise) 1.6e - (after CDS) (thermal noise) 26e - (after CDS) SWITCHER (kT/C)0.92nA 3.3e - CURO (sampling) 45nA 160e - External transamp. 26.5nA 94e - total: ~190e - (measured ~220e - ) … thermal 1/f noise after CDS switching noise:

24. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 24 - Test Beam Results Scintillator Telescope- Modules DEPFET System  Beam T24 @ DESY, Electrons @ 6 GeV  Reference telescope: 4 Si-strip planes noise ~ 16 ADU S/N ~110 (450µm sensors !) position resolution: CERN test beam in August 2006 [J.J. Velthuis, Bonn]

25. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 25 - zero suppressed matrix r/o works next CURO: neighbor logic zero suppressed matrix r/o lightspot of a desk lamp Hybrid with CMOS-Imager Matrix in AMS 0.35µm full analog frame zero suppressed analog readout [R.Kohrs, Bonn]

26. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 26 - summary current based readout for DEPFETs established  CURO II fabricated in TSMC 0.25µm attributes: - pedestal subtraction  suppresses sensor inhomogeniety - fast correlated double sampling  suppresses 1/f noise - on chip hit-detection and zero suppression performance: - noise: < 45nA   160 e - (depending on DEPFET amplification) - analog speed: 24 MHz line rate (48MSPS), sufficient for ILC ! - hit-identification and 0-suppression : > 100MHz, sufficient for ILC ! DEPFET system: - operated at  2MHz line rate - detection of X-Rays (10…50keV): INL: 0.75% - 6GeV e - testbeam at DESY: S/N  110 (450µm sensors)

27. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 27 - outlook CURO IIb: on-chip common mode computation/correction (easy with currents) cluster logic (keeping at least the closest neighbor) improve input cascode (readout larger matrices) implement (fast) power down feature (pulsed mode configuration) on chip ADC (IP from nordic semiconductor) System: increase system speed (2MHz  20MHz !!) reduce noise (190e - possible, next system should achieve <100e - ) References CURO / System: „Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector“, PhD thesis, M.Trimpl, http://hss.ulb.uni-bonn.de/diss_online Thinning: „Processing of ultra thin silicon sensors for future linear collider experiments“, L.Andricek et al., IEEE TNS (51), No3, pp.1117-1120 Sensor: „Design and Technology of DEPFET Pixel Sensors for Linear Collider Applicatons“, R.H.Richter, NIM A511, pp.250-256 Rad Tolerance: „The MOS-type DEPFET Pixel Sensor for the ILC Environment“, L.Andircek et al., Pixel 2005, submitted to NIM (A)

28. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 28 - Vorteil: - Null-Unterdrückung während Prozessierung einer Zeile - schnelles CDS (unterdrückt 1/f Rauschen) aber: - vollständiges „clear“ benötigt Auslesemodus: ILC ILC: kein „Trigger“  Null-Unterdrückung im Auslesechip „normal“ „ILC“

29. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 29 - Processing thin detectors - the Idea - d) anisotropic etching from backside (TMAH) open backside passivation c) process  passivation b) wafer bonding and grinding/polishing of top wafer a) oxidation and back side implant of top wafer Handle Wafer Top Wafer wafer bonding:dummy samples:

30. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 30 - source drain channel internal gate clear gate (Poly) clear (n + ) p-well high-E (some devices) DEPFET clear operation perpendicular to channelchannel view ‘clear gate’ to lower the clear barrier Clocked and static operation possible deep high-E n-implantation in some devices to lower clear voltages

31. FEE 2006, Perugia, 20.05.2006 Marcel Trimpl, University of Bonn - 31 - vertexing at the ILC frame: ~300µm sensor: ~50µm high spatial resolution  small pixels 20-30µm radiation tolerance (>200krad ionizing rad.) 50µm thin detector (excellent impact parameter resolution) low power (row-wise operation) high e + e - background: 80 hits / (mm 2 train)  detector readout (inner layer) in 50 µs baseline vtx-d design: DEPFET ladder: ‘holes’ to save material Thinned silicon sample (size ~ ILC ladder) Estimated total material budget: 0.11% X 0 / layer