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M. Szelezniak1PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensors Overview.

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Presentation on theme: "M. Szelezniak1PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensors Overview."— Presentation transcript:

1 M. Szelezniak1PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensors Overview

2 M. Szelezniak2PXL Sensor and RDO review – 06/23/2010 STAR Sensor Requirements Sensor requirements (consistent with IPHC development direction) ~2 cm x 2 cm (1 reticle) size. Pixel size < 30 µm. Integration time of ≤ 200 µs for L = 8 x cm -2 s -1 Power dissipation ≤ 170 mW/cm 2 (air cooling) Binary output with remote threshold adjustment Efficiency of ≥ 95% for MIPs with a simultaneous accidental noise rate of ≤ Maintain efficiency and accidental rate after radiation exposure of 90 kRad and MeV n eq / cm 2. ≤ 4 LVDS output channels (ladder space) Remote configuration

3 M. Szelezniak3PXL Sensor and RDO review – 06/23/2010 STAR Talk Outline IPHC Principle of operation Readout speed and integration time Radiation hardness PXL sensors development path Current generation of sensors Characteristics Testing results Next generation of sensors Sensor interface High resistivity substrate

4 M. Szelezniak4PXL Sensor and RDO review – 06/23/2010 STAR IPHC Principle of operation Readout speed and integration time Radiation hardness PXL sensors development path Current generation of sensors Characteristics Testing results Next generation of sensors Sensor interfaces High resistivity substrate

5 M. Szelezniak5PXL Sensor and RDO review – 06/23/2010 STAR Institut Pluridisciplinaire Hubert Curien IPHC-DRS (former IRES/LEPSI) proposed using MAPS for high energy physics in 1999 CMOS & ILC group today –6 physists –9 microcircuit designers –6 test engineers –7 PhD students CNRS - IPHC, Strasbourg-Cronenbourg More than 30 prototypes developed – several pixel sizes and architectures (simple 3-transistor cells, pixels with in-pixel amplifiers and CDS processing) – different readout strategies (sensors operated in current and voltage mode, analog and digital output) – Large variety of prototype sizes (from several hundreds of pixels up to 1M pixel prototype with full-reticule size) MIMOSA (Minimum Ionizing particle MOS Active sensor)

6 M. Szelezniak6PXL Sensor and RDO review – 06/23/2010 STAR Monolithic Active Pixel Sensors Standard commercial CMOS technology Room temperature operation Sensor and signal processing are integrated in the same silicon wafer Signal is created in the low-doped epitaxial layer (typically ~10-15 μm) → MIP signal is limited to <1000 electrons Charge collection is mainly through thermal diffusion (~100 ns), reflective boundaries at p-well and substrate → cluster size is about ~10 pixels (20-30 μm pitch)‏ 100% fill-factor Fast readout Proven thinning to 50 micron MAPS pixel cross-section (not to scale)‏

7 M. Szelezniak7PXL Sensor and RDO review – 06/23/2010 STAR Charge Sharing and Cluster Size Based on tests of several different prototypes S/N>12 allows detection efficiency >99.6% MimoSTAR2 test results (30 μm pixel pitch)

8 M. Szelezniak8PXL Sensor and RDO review – 06/23/2010 STAR MAPS Integration Time = Readout Time Typical sensor readout –Raster scan –Charge integration time = array readout time –Multiplexed sub-arrays to decrease integration time Column parallel readout architecture –All columns readout in parallel and then multiplexed to one output –Charge integration time = column readout time

9 M. Szelezniak9PXL Sensor and RDO review – 06/23/2010 STAR From Analog to Binary Readout Digital readout – offers increased speed but requires on-chip discriminators or ADCs and increased S/N for on-chip signal processing Analog readout – simpler architecture but slower readout

10 M. Szelezniak10PXL Sensor and RDO review – 06/23/2010 STAR MAPS – Ionizing Radiation

11 M. Szelezniak11PXL Sensor and RDO review – 06/23/2010 STAR MAPS – Non-ionizing Radiation

12 M. Szelezniak12PXL Sensor and RDO review – 06/23/2010 STAR IPHC Principle of operation Readout speed and integration time Radiation hardness PXL sensors development path Current generation of sensors Characteristics Testing results Next generation of sensors Sensor interfaces High resistivity substrate

13 M. Szelezniak13PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensors Development Path Pixel Sensors CDS ADC Data sparsification readout to DAQ analog signals Complementary detector readout MimoSTAR sensors 4 ms integration time PXL final sensors (Ultimate) < 200 μs integration time analog digital digital signals Disc. CDS Phase-1 sensors 640 μs integration time Sensor and RDO Development Path 1 2 3

14 M. Szelezniak14PXL Sensor and RDO review – 06/23/2010 STAR Current Generation of Sensors Phase-1 prototype Architecture based on Mimosa22 AMS-C35B4/OPTO which uses 4 metal- and 2 poly- layers 14 μm epitaxial layer Reticle size (~ 4 cm²) Pixel pitch 30 μm ~ 410 k pixels Column parallel readout Column discriminators Binary readout of all pixels Data multiplexed onto 4 LVDS 160 MHz Integration time 640 μs Functionality tests and yield look very good. Measured ENC is 15 e-. Beam test to measure MIP efficiency planned for Phase-2 prototype Small mask adjustments to improve discriminator threshold dispersion

15 M. Szelezniak15PXL Sensor and RDO review – 06/23/2010 STAR Phase1/2 Testing Results Discriminator transfer functions: Phase-1 FPN 0.6 mV to 1 mV temporal noise mV Phase-2 FPN ~0.5 mV temporal noise ~0.9 mV 55 Fe calibrations: noise ~14 e ─ ADC counts Threshold (mV) Column # Row # 1010 counts

16 M. Szelezniak16PXL Sensor and RDO review – 06/23/2010 STAR Phase 1 vs. Phase 2 In Phase-2 the magnitude of discriminator threshold variations is smaller than in Phase-1. Phase-1 chip B6 Phase-2 chip A2 Our test results feed back to IPHC designs to improve sensor performance

17 M. Szelezniak17PXL Sensor and RDO review – 06/23/2010 STAR Next Generation PXL Sensor Design based on Mimosa26 architecture Reticle size (~ 4 cm²) Pixel pitch 20.7 μm (recent change) 890 k pixels Reduced power dissipation Vdd: 3.0 V Optimized pixel pitch vs. Non-ionising radiation tolerance Estimated power consumption ~134 mW/cm² Short integration time μs Improved pixel architecture Optimized discriminator timing Improved threshold uniformity on-chip zero suppression 2 LVDS data 160 MHz Zero suppression circuitry (SUZE)

18 M. Szelezniak18PXL Sensor and RDO review – 06/23/2010 STAR Mimosa26

19 M. Szelezniak19PXL Sensor and RDO review – 06/23/2010 STAR On-chip Zero Suppression

20 M. Szelezniak20PXL Sensor and RDO review – 06/23/2010 STAR Data Format After Zero Suppression

21 M. Szelezniak21PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensor Testability

22 M. Szelezniak22PXL Sensor and RDO review – 06/23/2010 STAR Phase1 and Final PXL Sensor Interface Phase 1 and Phase 2Final PXL sensor Inputs LVDS/CMOS CLK JTAG: TCK, TMS, TDI, TDO, Reset START, SPEAK Vlcp (analog reference voltage) Outputs 8 x analog output 4 x LVDS2 x LVDS 16 x LVCMOS(?) LAST_ROW CLKD Test pad1, test pad2 DAC test pads (including Vref1, Vref2) Required “ladder” interface Required testing interface

23 M. Szelezniak23PXL Sensor and RDO review – 06/23/2010 STAR IPHC Principle of operation Readout speed and integration time Radiation hardness PXL sensors development path Current generation of sensors Characteristics Testing results Next generation of sensors Sensor interfaces High resistivity substrate

24 M. Szelezniak24PXL Sensor and RDO review – 06/23/2010 STAR New Prototype on High Resistivity Substrate

25 M. Szelezniak25PXL Sensor and RDO review – 06/23/2010 STAR Sensor performance with HR substrate

26 M. Szelezniak26PXL Sensor and RDO review – 06/23/2010 STAR Summary Sensor performance satisfies requirements Sensors design at IPHC is on schedule High resistivity substrate dramatically improves S/N and removes radiation hardness issues The design of the final PXL sensor will benefit from the ongoing tests of Mimosa22HR and latch up tests of Mimosa22HR and memory prototypes planned later this year Phase-2 will be used for ladder prototyping We will build a 3-sector detector prototype equipped with Phase-2 sensors to test it at STAR (2012)

27 M. Szelezniak27PXL Sensor and RDO review – 06/23/2010 STAR Backup slides

28 M. Szelezniak28PXL Sensor and RDO review – 06/23/2010 STAR Phase1/2 testing results The Phase-1 performance tested on several chips1 demonstrated FPN ranging from 0.6 mV to 1 mV and temporal noise estimated at mV.

29 M. Szelezniak29PXL Sensor and RDO review – 06/23/2010 STAR MAPS principle of operation Continuous reverse bias (self-biased) Classical diode with reset Reset noise, offset No reset noise, no offset read

30 M. Szelezniak30PXL Sensor and RDO review – 06/23/2010 STAR Sensor/RDO Requirements by generation Mimostar–2 30 µm pixel, 128 x 128 array 1.7 ms integration time 1 analog output Mimostar–3 30 µm pixel, 320 x 640 array 2.0 ms integration time 2 analog outputs Phase–1/2 30 µm pixel, 640 x 640 array 640 µs integration time, CDS 4 binary digital outputs Final (Ultimate) 18.4 µm pixel, 1024 x 1088 array ≤ 200 µs integration time, CDS, zero suppression 2 digital outputs (addresses) SensorSensor RDO 50 MHz readout clock JTAG interface, control infrastructure ADCs, FPGA CDS & cluster finding zero suppression ≤ 4 sensor simultaneous readout 160 MHz readout clock JTAG interface, control infrastructure zero suppression 120 sensor simultaneous readout 160 MHz readout clock JTAG interface, control infrastructure 400 sensor simultaneous readout (full system) DONE PROTOTYPED Gen


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