1. 1 CzajkowskiMAPLD 2005/138 Radiation Hardened, Ultra Low Power, High Performance Space Computer Leveraging COTS Microelectronics With SEE Mitigation D. Czajkowski, D. Strobel, P. Samudrala, and M. Pagey Space Micro Inc., 10401, Roselle St., Suite 400 San Diego, CA 92121 Ph: 858-332-0701

2. 2 CzajkowskiMAPLD 2005/138 ➢ Why use COTS microprocessors (MP) for space computers? ➢ TTMR for SEU mitigation ➢ Hardened Core (H-Core) for SEFI mitigation ➢ Proton-100k Space Computer ➢ Roadrunner Flight Experiment ➢ Summary and Future Plans Overview

3. 3 CzajkowskiMAPLD 2005/138 Why use COTS Microprocessors for space computers? ➢ Commercial Microprocessors (MP) have high performance, lower cost, lower area, and consume lesser power compared to space qualified MPs ➢ User has a range of COTS MP's to choose from ➢ Downside : Poor performance under radiation (in space) ➢ New technologies proposed in this paper resolve those issues ➢ Hardware-Software approach used for SEUs and SEFI mitigation

4. 4 CzajkowskiMAPLD 2005/138 Time-Triple Modular Redundancy (TTMR) Technique : Overview ➢ Combines Time and Hardware redundancy techniques ➢ Runs redundant instructions on different ALUs of VLIW processor ➢ Results compared intermittently ➢ Program executes normally if results match or ➢ Time redundancy used in running the third version ➢ Results of all 3 computations voted to obtain the right result

5. 5 CzajkowskiMAPLD 2005/138 TTMR Technique ➢ TTMR can be applied at program level or at instruction level ➢ TTMR at instruction level has several advantages over program level implementation ✔ Instructions can be used to direct different versions to separate ALUs ✔ An SEU can be detected and corrected immediately ➢ TTMR at instruction level is being used by Space Micro.

6. 6 CzajkowskiMAPLD 2005/138 TTMR Precompiler ➢ TTMR incorporates several other procedures for effective SEU mitigation ➢ A “Precompiler” could be used for automatic insertion of TTMR ➢ User provided an option of choosing 1 of the 4 algorithms of inserting TTMR ➢ The algorithms are referred to as 1.1, 1.2, 2.1, and 2.2

7. 7 CzajkowskiMAPLD 2005/138 TTMR Flow High Level (C / C++) input program Space Micro's Pre-compiler TTMR Algorithm TTMR'd input program ➢ Pre-compiler inserts TTMR ➢ Modifications made according to the algorithm selected ➢ The output program is SEU hardened !

8. 8 CzajkowskiMAPLD 2005/138 ➢ 3 radiation tests completed to estimate the performance of TTMR ➢ Results suggest that TTMR has 100% SEU coverage ➢ Equator Technologies BSP-15 microprocessor chosen as a very favorable processor for implementing TTMR ➢ BSP-15 is being currently used in Space Micro's single board computers TTMR performance

9. 9 CzajkowskiMAPLD 2005/138 ➢ SEFI Characteristics ✔ Processor Hangs Suddenly ➢ Probable causes of “Hangs” ✔ Illegal branching ✔ Upsets in program counter of the CPU ✔ Jumps to undefined/test states ➢ Approx. rates : 1 per 100 days for SOI Power PC and 1per 10 for CMOS version ➢ Current solution to power cycle the system ➢ Results in unnecessary delays and data loss SEFIs in Microprocessors

10. 10 CzajkowskiMAPLD 2005/138 ➢ H-Core ✔ Combination of Software and Hardware ✔ Monitors CPU Functionality ✔ Stores rollback information ✔ Detects and indicates SEFI occurrences ✔ Revives CPU from SEFI events ➢ H-Core ✔ Sends CPU alive messages ✔ Saves periodic roll-back information ✔ Reads SEFI indicator from H-Core chip, and ✔ Recovers running processes after SEFI events H-Core Technique CPU Bus Controller Memory Ethernet SCSI HBA H-Core Chip

11. 11 CzajkowskiMAPLD 2005/138 The H-Core Chip ➢ Manufactured using rad-hard components ➢ Usable with any processor ➢ Provides min. 8 interrupt signals ➢ Uses MOSFET driver for power cycle ➢ Provides variable levels and pulse widths of interrupts ➢ Contains programmable CPU check timer ➢ Sets SEFI status signal for SEFI recovery software ➢ Provides external reset control

12. 12 CzajkowskiMAPLD 2005/138 H-Core Performance ➢ Radiation Tests on three different processors were performed ✔ Pentium P-III ✔ TI TMS320C6713 DSP ✔ Equator BSP-15 DSP ➢ Each processor was irradiated to induce a SEFI and H-Core circuit was then used in mitigating the SEFI ➢ H-Core was able to mitigate all the SEFIs without powering down the target board

13. 13 CzajkowskiMAPLD 2005/138 ➢ Proton 100k computer is based on the technologies discussed above: ✔ Time Triple Modular Redundancy (TTMR) for SEU mitigation ✔ Hardened Core (H – Core) for SEFI mitigation ➢ The projected performance of the Proton 100k is as shown below: ✔ Over 1200 MIPS ✔ Less than 1 X 10 -4 uncorrected SEUs ✔ SEFI mitigation using H-Core Chip ✔ No Single Event Latchup ✔ Total dose rates greater than 95krad (Si) Proton 100k computer

14. 14 CzajkowskiMAPLD 2005/138 ➢ Proton 100k is being used in several applications ➢ The first prototype of proton 100k is being used by AFRL in Roadrunner experiment ➢ Another modified version has been adapted for use in International Space Station (ISS) medical equipment ➢ Proton *00 k are also being used in the DARPA's Falcon and MDA's MISTI projects ➢ Space Micro is currently developing the technology for DSP applications employing FPGAs Proton 100k computer

15. 15 CzajkowskiMAPLD 2005/138 Proton 100k computer

16. 16 CzajkowskiMAPLD 2005/138 ➢ Space Micro's Proton 100k computer using TTMR has the ability to detect and correct 100% of the induced SEUs ➢ However, SEFIs are not covered by TTMR ➢ SEFIs are mitigated using H-Core. ➢ H-Core has been demonstrate to perform excellently under radiation and was able to mitigate SEFIs in all the cases ➢ Incorporating Space Micro's H-Core circuit can provide complete protection against SEUs and SEFIs ➢ Proton 100k computer built on TTMR and H-Core technologies has superior performance and excellent radiation hardness ➢ Proton 100k outperforms computers using TMR'd microprocessors or computers using time redundancy ➢ Proton 100k is also estimated to have performance greater than or equal to that of space computers built on radiation hardened process Summary