Presentation is loading. Please wait.

Presentation is loading. Please wait.

Erik Jonsson School of Engineering & Computer Science Redundant SAR ADC Architecture and Circuit Techniques for ATLAS LAr Phase-II Upgrade Ling Du 1, Hongda.

Published byAlyson Sullivan Modified over 8 years ago

Similar presentations

Presentation on theme: "Erik Jonsson School of Engineering & Computer Science Redundant SAR ADC Architecture and Circuit Techniques for ATLAS LAr Phase-II Upgrade Ling Du 1, Hongda."— Presentation transcript:

1 Erik Jonsson School of Engineering & Computer Science Redundant SAR ADC Architecture and Circuit Techniques for ATLAS LAr Phase-II Upgrade Ling Du 1, Hongda Xu 1, Yun Chiu 1 Datao Gong 2, Jingbo Ye 2 1 University of Texas at Dallas, Richardson, TX, USA 2 Southern Methodist University, Dallas, TX, USA

2 TWEPP 2015- 2 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single-Event-Effect (SEE) Protection Layout and Simulation Results Summary

3 TWEPP 2015- 3 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single-Event-Effect (SEE) Protection Layout and Simulation Results Summary

4 TWEPP 2015- 4 -2015-10-01 ADC Specs for Phase-II LAr Readout High resolution: 12-14 bits High speed: 40-80 MS/s Low power, low area Radiation-tolerant Detector Output Signal Phase-II Upgrade FEB (On detector) MUX & Serializer MUX & Serializer Optical Links To Back-end Analog Shaper … ADC … Preamp … ADC 16-bit DR10 Gbps???

5 TWEPP 2015- 5 -2015-10-01 Previous TID Results (TWEPP’14) 12-bit, 160-MS/s ADC on 40-nm CMOS Total radiation dose up to 1 Mrad No significant degradation on SNDR, SFDR

6 TWEPP 2015- 6 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single Event Effect (SEE) Protection Layout and Simulation Results Summary

7 TWEPP 2015- 7 -2015-10-01 LMS update: Architecture – Split ADC Split-ADC enables digital background calibration

8 TWEPP 2015- 8 -2015-10-01 Fewer number of bits in first stage Amplifier removed from SAR Loop Fast Conversion Architecture – Pipelined SAR 9 bits7 bits

9 TWEPP 2015- 9 -2015-10-01 Architectural Redundancies Sub-binary DAC RA gain reduction and inter-stage redundancy Intra-stage and inter-stage redundancies for dynamic error tolerance DAC incomplete settling, reference voltage bouncing, etc. Comparator hysteresis, noise crosstalk, etc.

10 TWEPP 2015- 10 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single-Event-Effect (SEE) Protection Layout and Simulation Results Summary

11 TWEPP 2015- 11 -2015-10-01 Split ADC for SEE Protection If ΔD o is large, chose the output of the ADC that is not hit A 3-dB SNR gain with normal operation (i.e., no hit)

12 TWEPP 2015- 12 -2015-10-01 Modeling SEE Current Ref. Bonacini, “Redundancy methods in ASICs,” 2013 Ref. Mavis and Eaton, “SEU and SET Modeling and Mitigation in Deep Submicron Technologies,” 2007

13 TWEPP 2015- 13 -2015-10-01 Summing-Node Hit Detection For Q SEE = 100 fC and C TOT = 2 pF, V err = 50 mV ! SEE detector is formed by a pair of resistors, a “substrate- current amplifier”, and some digital logic

14 TWEPP 2015- 14 -2015-10-01 Summing-Node Hit Detection I SEE CLK_samp SEE_Amp SEE_Out The total charge collected due to SEE is ~5.5 fC, causing a 2.75-mV voltage error on a 2-pF DAC (~20 LSBs) The detector is reset at the beginning of each sample period 0.6V 0.97V

15 TWEPP 2015- 15 -2015-10-01 1 st -Stage SAR Error Detection Out-of-range error can be detected by observing the code of the 2 nd stage: 11…11 (overshoot) or 00…00 (undershoot)

16 TWEPP 2015- 16 -2015-10-01 2 nd -Stage SAR Error Detection

17 TWEPP 2015- 17 -2015-10-01 Data-Latch Error Detection

18 TWEPP 2015- 18 -2015-10-01 Data-Latch Error Detection Data latches hit during residue amplification may cause error

19 TWEPP 2015- 19 -2015-10-01 Data-Latch Error Detection

20 TWEPP 2015- 20 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single-Event-Effect (SEE) Protection Layout and Simulation Results Summary

21 TWEPP 2015- 21 -2015-10-01 Layout Screenshot 65-nm CMOS

22 TWEPP 2015- 22 -2015-10-01 Preliminary Simulation Results CornerMax. Fs [MS/s]SNDR [dB]SFDR [dB] TT (w/o noise)10086.599.9 SS (w/o noise)8086.499.2 FF (w/o noise)10086.9101.8 TT (w/ noise)100 76.4, single 79.1, avg 93.3, single 95.3, avg TT w/o circuit noise

23 TWEPP 2015- 23 -2015-10-01 Outline Introduction ADC Architecture and Redundancy Single-Event-Effect (SEE) Protection Layout and Simulation Results Summary

24 TWEPP 2015- 24 -2015-10-01 Summary Redundant pipelined SAR ADC is a strong candidate to meet the stringent requirements for ATLAS LAr upgrade Split-ADC architecture with SEE detection techniques provides a potential (architecture + analog) solution to SEE Various SEE-protection techniques and proven TID-tolerance will result in a fully radiation-tolerant ADC in CMOS in the near future Stay tuned… Thank you for your attendance!

25 TWEPP 2015- 25 -2015-10-01 Backup Slides

26 TWEPP 2015- 26 -2015-10-01 Split-ADC Bit-Weight Calibration Offset injection to the SAR conversion curve to split the decision trajectory

27 TWEPP 2015- 27 -2015-10-01 Behavioral Simulation Results Calibration converges within 1 million samples [MSamples] [dB]

28 TWEPP 2015- 28 -2015-10-01 Comparator-RA Offset 150-mV 2 nd -stage full scale 2-bit inter-stage redundancy 16× inter-stage gain Maximum tolerable offset: Too small ! Observing the digital code of the 2 nd stage enables residue confinement

29 TWEPP 2015- 29 -2015-10-01 Comparator-RA Offset Calibration Auxiliary DAC used to compensate the comparator-RA offset

30 TWEPP 2015- 30 -2015-10-01 TMR Protection for Logic Gates TMR-protected shift registers are used in other parts, i.e., clock generation, parallel-to-serial conversion, etc.

Download ppt "Erik Jonsson School of Engineering & Computer Science Redundant SAR ADC Architecture and Circuit Techniques for ATLAS LAr Phase-II Upgrade Ling Du 1, Hongda."

Similar presentations

HIPPO, a Flexible Front-End Signal Processor for High-Speed Image Sensor Readout Carl Grace, Dario Gnani, Jean-Pierre Walder, and Bob Zheng June 10, 2011.

HIPPO, a Flexible Front-End Signal Processor for High-Speed Image Sensor Readout Carl Grace, Dario Gnani, Jean-Pierre Walder, and Bob Zheng June 10, 2011.
CMOS Comparator Data Converters Comparator Professor Y. Chiu

CMOS Comparator Data Converters Comparator Professor Y. Chiu
– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC.

– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC.
Digital to Analog and Analog to Digital Conversion

Digital to Analog and Analog to Digital Conversion
Announcements Assignment 8 posted –Due Friday Dec 2 nd. A bit longer than others. Project progress? Dates –Thursday 12/1 review lecture –Tuesday 12/6 project.

Announcements Assignment 8 posted –Due Friday Dec 2 nd. A bit longer than others. Project progress? Dates –Thursday 12/1 review lecture –Tuesday 12/6 project.
Fischer 08 1 Analog to Digital Converters Nyquist-Rate ADCs  Flash ADCs  Sub-Ranging ADCs  Folding ADCs  Pipelined ADCs  Successive Approximation.

Fischer 08 1 Analog to Digital Converters Nyquist-Rate ADCs  Flash ADCs  Sub-Ranging ADCs  Folding ADCs  Pipelined ADCs  Successive Approximation.
Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State.

Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.

FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
18/05/2015 Calice meeting Prague 2007 1 Status Report on ADC LPC ILC Group.

18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.
Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.

Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.
DNC, GEC & Non-linear Interpolation DNC, GEC & Non-linear interpolation A Review of ”A Digitally Enhanced 1.8V 15-bit 40-MSample/s CMOS.

DNC, GEC & Non-linear Interpolation DNC, GEC & Non-linear interpolation A Review of ”A Digitally Enhanced 1.8V 15-bit 40-MSample/s CMOS.
A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization Time-interleaved ADC array –High sampling rate, low power.

A 600MS/s 30mW 0.13µm CMOS ADC Array Achieving over 60dB SFDR with Adaptive Digital Equalization Time-interleaved ADC array –High sampling rate, low power.
Introduction to Analog-to-Digital Converters

Introduction to Analog-to-Digital Converters
1 A 16:1 serializer for data transmission at 5 Gbps Datao Gong 1, Suen Hou 2, Zhihua Liang 1, Chonghan Liu 1, Tiankuan Liu 1, Da-Shun Su 2, Ping-Kun Teng.

1 A 16:1 serializer for data transmission at 5 Gbps Datao Gong 1, Suen Hou 2, Zhihua Liang 1, Chonghan Liu 1, Tiankuan Liu 1, Da-Shun Su 2, Ping-Kun Teng.
Development of novel R/O electronics for LAr detectors 6.10.2006 Max Hess Controller ADC Data Reduction Ethernet 10/100Mbit Host Detector typical block.

Development of novel R/O electronics for LAr detectors Max Hess Controller ADC Data Reduction Ethernet 10/100Mbit Host Detector typical block.
1 SciFi electronics meeting – CERN– June 20 th 2011 Some ideas about a FE for a SciFi tracker based on SiPM A. Comerma, D. Gascón Universitat de Barcelona.

1 SciFi electronics meeting – CERN– June 20 th 2011 Some ideas about a FE for a SciFi tracker based on SiPM A. Comerma, D. Gascón Universitat de Barcelona.
A 10 bit,100 MHz CMOS Analog- to-Digital Converter.

A 10 bit,100 MHz CMOS Analog- to-Digital Converter.
Status of opto R&D at SMU Jingbo Ye Dept. of Physics SMU For the opto WG workshop at CERN, March 8 th, 2011.

Status of opto R&D at SMU Jingbo Ye Dept. of Physics SMU For the opto WG workshop at CERN, March 8 th, 2011.
Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.

Motivation Yang You 1, Jinghong Chen 1, Datao Gong 2, Deping Huang 1, Tiankuan Liu 2, Jingbo Ye 2 1 Department of Electrical Engineering, Southern Methodist.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.

FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.

Similar presentations

Ads by Google