2. Specifications Asic description Constraints Interface with PDM board Schedule Summary

3. 3 ASICs Connector Rigid from EC-ANODE Connector toward the PDM board As close as possible Flex from EC-ANODE Specifications: An ASIC is assigned to each MAPMT  36 ASICs have to be distributed on the boards of the EC-back electronic. They should also include the connectors toward the EC-anode and PDM boards as well as all the passive components needed. The idea is to go for 6 boards (3 pairs of boards facing each other) perpendicular to the PDM mechanical structure. Volume for Electronics: EC_asic, HV box, PDM board PDM Frame With EC_front MAPMT

4. ASIC BASIC FASIC D 4 3 ASICs, with their associated passive components, on each side of the pcb 6 connectors (68 pins: 64 anodes + 4 gnd) on top side 1 connector (120 pins) on top side 68 pins68 pins ASIC A 68 pins68 pins ASIC C ASIC E 120 pins ABCDEF 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins

5. 5 Specifications:  Readout MAPMT signals  Consumption: 1mW/channel  Photon counting: 100% trigger efficiency@50fC (1/3pe, 10 6 Gain)  Charge/time converter input range : 2pc – 200pc (10pe - 1000pe)  Radiation hardness Spatial Photomultiplier Array Counting and Integrating ReadOut Chip 1st version received in October 2010 Technology: AMS 0.35µm SiGe Dimensions : 4.6mm x 4.1mm (19 mm²) Power supply: 0-3V Packaging : P(C)QFP240(160)

6. 6 64 channels Preamplifier with individual 8-bit gain adjustment Photo-electron counting (10-bit DACs) – 3 discriminator outputs : Trig_PA, Trig_FSU & Trig_VFS – Multiplexed discriminator outputs to Digital part – Many parameters available Charge to time converters (called KIs) – Designed in collaboration with JAXA/RIKEN – 9 outputs : 8 channels (8-pixel-Sum) + Last Dynode – Many parameters available Continuous Data acquisition & Readout every 2.5  s (GTU) – 8 identical digital module for PC – 1 digital module for KI First version of SPACIROC showed good behavior (intensive lab tests with and without MAPMT)

7. 7 Package: CQFP 160pins by MATRA Quantity: 100 Cost: 105€/asic Delay: – Package material : 2 weeks – 3 prototypes: 2 weeks – 100 asics: 2 weeks One test board has been produced to sort chips – Cabling ok – Firmware is the same as the previous spaciroc test board – Software should be modified to perform automatic tests

8. 2 types of pcbs are foreseen: 8 1 with a straight flexible part Connector on top 1 with a curved flexible part Connector on bottom

9. 9 Connectors choice: EC_asic: HIROSE FX2CA-68S-1.27DSA - Receptacle - Dimension=49mm x 7.5mm - Straight type - Through hole type Not exactly the same pinout for the 2 types of EC_anode => For EC_asic design, we need to know which connector corresponds to which type of EC_anode

10. 10 3 EC_unit + 2 EC_ASIC boards – Curved EC_anodes: connectors A, C, E – Straigth EC_anodes: connectors B, D, F One EC_asic reads half of the EC_unit 12345678 5749413325179112345678 5749413325179112345678 57494133251791 9101112131415165850423426181029 1112131415165850423426181029 111213141516585042342618102 171819202122232459514335271911317181920212223245951433527191131718192021222324595143352719113 252627282930313260524436282012425262728293031326052443628201242526272829303132605244362820124 333435363738394061534537292113533343536373839406153453729211353334353637383940615345372921135 414243444546474862544638302214641424344454647486254463830221464142434445464748625446383022146 495051525354555663554739312315749505152535455566355473931231574950515253545556635547393123157 5758596061626364 56484032241685758596061626364 56484032241685758596061626364 5648403224168 8 243240485664 63626160595857816243240485664 63626160595857816243240485664 63626160595857 715233139475563565554535251504971523313947556356555453525150497152331394755635655545352515049 614223038465462484746454443424161422303846546248474645444342416142230384654624847464544434241 513212937455361403938373635343351321293745536140393837363534335132129374553614039383736353433 412202836445260323130292827262541220283644526032313029282726254122028364452603231302928272625 311192735435159242322212019181731119273543515924232221201918173111927354351592423222120191817 2101826344250581615141312111092 1826344250581615141312111092 182634425058161514131211109 19172533414957 8765432119172533414957 8765432119172533414957 87654321 Pmt 1 Pmt 3 Pmt 2 Pmt 4 B CD A EF FE A DC B

11. Ki input: sum of 8 consecutive anodes 11 12345678 5749413325179112345678 5749413325179112345678 57494133251791 9101112131415165850423426181029 1112131415165850423426181029 111213141516585042342618102 171819202122232459514335271911317181920212223245951433527191131718192021222324595143352719113 252627282930313260524436282012425262728293031326052443628201242526272829303132605244362820124 333435363738394061534537292113533343536373839406153453729211353334353637383940615345372921135 414243444546474862544638302214641424344454647486254463830221464142434445464748625446383022146 495051525354555663554739312315749505152535455566355473931231574950515253545556635547393123157 5758596061626364 56484032241685758596061626364 56484032241685758596061626364 5648403224168 8 243240485664 63626160595857816243240485664 63626160595857816243240485664 63626160595857 715233139475563565554535251504971523313947556356555453525150497152331394755635655545352515049 614223038465462484746454443424161422303846546248474645444342416142230384654624847464544434241 513212937455361403938373635343351321293745536140393837363534335132129374553614039383736353433 412202836445260323130292827262541220283644526032313029282726254122028364452603231302928272625 311192735435159242322212019181731119273543515924232221201918173111927354351592423222120191817 2101826344250581615141312111092 1826344250581615141312111092 182634425058161514131211109 19172533414957 8765432119172533414957 8765432119172533414957 87654321 Pmt 1Pmt 2 B CD A EF FE A DCB To check the routing feasibility: Schematic simpler: 2 connectors: connector A (curved kapton) and connector B (straight kapton) 2 SPACIROC Connector 120pins ki1ki2 ki3ki4 ki3 ki2ki1 ki2ki6 ki1ki5 ki1 ki6ki2 ki1ki2 ki3ki4 ki1ki2 ki3ki4 ki5ki1 ki6ki2 ki5ki1 ki6ki2 ki4ki3 ki2ki1 ki3 ki2ki1 ki2ki6 ki1ki5 ki2ki6 ki1ki5 ki4

12. 12 The ASIC: SPACIROC (2/3)

13. 13

14. Dimension could be 140mm x 110mm

15. Modifications: – Vertical red parts should be modified Increase area for EC_ASIC boards – Support structures have to be aligned with the holes like the central one otherwise cables do not pass – Find room for the HV box boards 15 Material: Aluminum Weight: 0.300 kg Overall dimensions: 167mm x 128mm x 130mm Available area for elect. : 115mm x 100mm => not enough ~ 55 mm As short as possible Pair of EC- ASIC boards Need to study how to screw the boards: EC_asic, HV box boards and PDM board 130 167 128

16. Connector 120 pins should be enough Choice: HIROSE FX2-120P-1.27DS – Header – Dimension=82mm x 7.5mm – Right angle type – Through hole 16 Input name and number of pinsOutput name and number of pins avdd4Sr_ck1Clk_40n1Adata_ki1Atransmit_on1Adata_pc[7..0]8AOR_ki_sum1Aerror_sc1 vdd_ki2Sr_in1Clk_40p1Bdata_ki1Btransmit_on1Bdata_pc[7..0]8BOR_ki_sum1Berror_sc1 dvvd4sr_out1Clk_gtu_n1Cdata_ki1Ctransmit_on1Cdata_pc[7..0]8COR_ki_sum1Cerror_sc1 VH4Sr_rstb1Clk_gtu_p1Ddata_ki1Dtransmit_on1Ddata_pc[7..0]8DOR_ki_sum1Derror_sc1 gnd14resetb1Val_evt_n1Edata_ki1Etransmit_on1Edata_pc[7..0]8EOR_ki_sum1Eerror_sc1 Select_sc_probe1Val_evt_p1Fdata_ki1Ftransmit_on1Fdata_pc[7..0]8FOR_ki_sum1Ferror_sc1 Loadb_sc1AOR_FSU1COR_FSU1EOR_FSU1 Select_din1BOR_FSU1DOR_FSU1FOR_FSU1 What will be the connection between the EC_ASIC and the PDM board? Kapton or cable ? Who is in charge of this connection

17. Week 9: 24 Jan-3 Feb – Feasibility routing inputs with 2 through hole connectors Week 10: 5 -9 Mar – Feasibility routing inputs with 2 surface mounted connectors – Schematic of whole EC_asic Week 11-14: 12 Mar- 6Apr – Routing whole EC_asic => the dimensions will be set – Schematic of a test board (test_ec_asic) to check functionalities of one EC_ASIC Week 15-16: Easter holidays Week 17-21: 23 Apr- 25May – Routing test_ec_asic board 17 Production PCBs will be done when the money is available Cabling and component procurement will be managed by us

18. LAL team manage schematic, routing and production of EC_ASIC boards Dimension could be as low as 140mm x 110mm (routing will be checked) To Be Defined: – Who can do the mechanical modifications? – Who is in charge of the connection between EC_ASIC and the PDM board (lack of manpower and time at LAL)? 18