1. The EC-UNIT P. Barrillon on behalf of JEM-EUSO collaboration EUSO-BALLOON Phase A review 2 nd February 2012, CNES, Toulouse

2. Outline What is the EC unit ? Technical specifications + requirements Description of the EC unit – List of components – Individual description of each component Risk analysis Development plan + planning 2

3. EC stands for Elementary Cell It consists in 4 Multi-Anode Photo-Multiplier Tubes (MAPMTs) of 64 channels grouped as a 2x2 matrix It also contains the front end electronic chain that shall collect the MAPMTs’ output signals and process them Moreover it shall welcome the piece of electronic needed to provide the high voltage to the MAPMTs What is the EC unit ? 3

4. Each EC unit should include 4 MAPMTs as well as the pieces of electronic needed to supply the High Voltage to them and collect the signals from them It should fit in the space dedicated in the PDM mechanical structure 14 different High Voltages should be provided to each MAPMT of 1 EC unit Signals from the MAPMT should be readout by SPACIROC ASIC SPACIROC should – do the signal measurement of the 64 MAPMT channels – perform photoelectron counting and charge/time integration respectively for low and high photon flux – provide digital output signals Digital data coming out of each EC should be sent to the PDM board for treatment Parts sensitive to sparking should be potted or coated MAPMTs should be equipped of a BG3 UV filter to select the N2 fluorescence photons (290 – 430 nm) Technical specifications and requirements 4

5. MAPMTs EC-Front (stack of 3 pcbs) – EC-dynode board – EC-anode boards (2 types) – EC-HV board EC-Back – EC-ASIC board – SPACIROC ASIC HV Box (see P.G’s talk) – Cockroft-Walton – Switches EC unit description: all the components 5

6. The MAPMT: description 6 R11265-M64 MAPMT from Hamamatsu. – 64 channels (Anodes) – 12 Dynodes (Dy1 – Dy12), 1 cathode (K) and 1 Guard Ring (GR) It is a photo-detector used to sense the UV photons arriving through the lenses. Each one should be equipped with a UV filter bonded with an optical glue Its gain range is 30 to 10 6 with a non-uniformity between channels of 1:3

7. The MAPMT: level of the voltages NC K (1000 V) GR (20 V) Dy1 (805) Dy2 (738) Dy3 (671) Dy4 (604) Dy5 (537) Dy6 (470) Dy7 (403) Dy8 (336) Dy9 (268) Dy10 (201) Dy11 (134) Dy12 (67) Ch1 Ch8 Ch9 ch64 K GR Bottom view 7

8. 3 different PCBs: First one (EC DYNODE board) allows to reroute half of the dynodes of 1 MAPMT so that they are aligned perpendicularly to the others. It covers the 4 MAPMTs. Second one (EC ANODE board) covers one MAPMT but has dimensions reduced allowing a flex pcb to get out. It is used to collect signal from the anodes and send them to the ASICs. Third one (EC HV board) covers one MAPMT. It welcomes the dynodes and supplies the HV to the EC-dynode board which transmits it to the 4 MAPMTs. EC unit description: front part Per EC unit: 1 EC-DYNODE board 4 EC-ANODE boards 1 EC-HV boards UV filter MAPMT Flexible pcb toward EC-back HV cables toward HV box 8

9. EC-Unit: side view MAPMT EC ANODE BOARD EC DYNODE BOARD EC HV BOARD dynode anode EC-ASIC board welcomes ASICs as well as connectors. Data out are then transmitted to the PDM board. Toward PDM board 9

10. PCB used to transmit HV signals to the dynodes pins of each MAPMT. Rerouting will have to be done for 7 pins (GR and Dy7 to Dy12) of one MAPMT For the MAPMTs with no rerouting: all 14 pins (K, GR and Dy1 to Dy12) will be cut and soldered on this pcb For the MAPMT with rerouting: the 6 dynodes with lowest voltages and GR will be rerouted, new pins will be soldered on the pcb with the proper length. The 7 other pins (Dy1 to Dy6 and K pin) will have extensions added The EC-dynode board 64 anodes pins going through the pcb (no soldering/connection) Rerouting of 6 HV pins and GR 10

11. The EC-anode board (1/3) EC-ANODE corresponding to the MAPMT with rerouted pins at the level of the EC-dynode board. Bigger holes because of extensions Same PCBs (holes for dynodes are not represented) Holes through which will go the new pins of the EC-DYNODE board (6 represented but they need to be 7) Extensions Areas gained for flexes 11

12. Allows the routing of the 64 signals toward the connector. Choice of the connector is the critical part. It shouldn’t be too high, too large or too long but has to allow a feasible routing. The EC-anode board (2/3) 12 Flexible pcb Rigid pcb As long as needed connector 23.7 mm ~ 24 mm 23.7 mm

13. 2 types of pcbs are foreseen: 1 with a straight flexible part 1 with a curved flexible part Only the shape of the flexible part would differ (same routing, same orientation/location of the connector) Easier assembly The EC-anode board (3/3) 13 CONNECTORCONNECTOR connector

14. Simple multi-layer rigid pcb It welcomes – 14 HV cables coming from the HV box – 14 pins coming from the EC-dynode Routing of the HV lines should follow isolation rules and each line will have a connector at mid point between HV-box and EC-HV board. The EC-HV board 14

15. From EC-front to EC-back 15 The flex and second rigid parts of the EC-anode boards have to go through the mechanical structure to reach the EC-ASIC board. PDM mechanical structure, with cross and hole.

16. The EC-ASIC board (1/4) 16 ASICs Connector Rigid from EC-ANODE Connector toward the PDM board As close as possible Flex from EC-ANODE Specifications: An ASIC is assigned to each MAPMT  36 ASICs have to be distributed on the boards of the EC-back electronic. They should also include the connectors toward the EC- anode and PDM boards as well as all the passive components needed. The idea is to go for 6 boards perpendicular to the PDM mechanical structure. A pair of boards for each group of 3 EC units. They would be fixed on a mechanical structure perpendicular to the one of the PDM Each board would have 6 connectors (toward EC-anode boards) and 6 ASICs, many passive components and 1 connector toward PDM board.

17. The EC-ASIC board (2/4) 17 3 ASICs, with their associated passive components, on each side of the pcb 6 connectors (68 channels) on one side 1 connector (120 pins) ASIC 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins 68 pins68 pins At least 120 mm needed. ~40 mm ~ 60 mm ~ 20 mm ~ 150 mm 120 pins

18. The EC-ASIC board (3/4) 18 Additional mechanical structure Pair of EC- ASIC boards ~ 55 mm As short as possible

19. The EC-ASIC board (4/4) 19 3 top views at different heights. Packaged ASIC EC-ANODE rigid part Pair of EC-ASIC boards Additional mechanical structure Connector from EC-anode Connector toward PDM board

20. The ASIC: SPACIROC (1/2) 20 Specifications:  Readout MAPMT signals  Consumption: 1mW/channel  Photon counting: 100% trigger efficiency@50fC (1/3pe, 10 6 Gain)  Charge/time converter input range : 2pc – 200pc (10pe - 1000pe)  Radiation hardness Spatial Photomultiplier Array Counting and Integrating ReadOut Chip 1st version received in October 2010 Technology: AMS 0.35µm SiGe Dimensions : 4.6mm x 4.1mm (19 mm²) Power supply: 0-3V Packaging : P(C)QFP240(160)

21. The ASIC: SPACIROC (2/2) 21 64 channels Preamplifier with individual 8-bit gain adjustment Photo-electron counting (10-bit DACs) – 3 discriminator outputs : Trig_PA, Trig_FSU & Trig_VFS – Multiplexed discriminator outputs to Digital part – Many parameters available Charge to time converters (called KIs) – Designed in collaboration with JAXA/RIKEN – 9 outputs : 8 channels (8-pixel-Sum) + Last Dynode – Many parameters available Continuous Data acquisition & Readout every 2.5  s (GTU) – 8 identical digital module for PC – 1 digital module for KI First version of SPACIROC showed good behavior (intensive lab tests with and without MAPMT)

22. The HV box 22 One or two per PDM (depending on size, prototype pending) Houses the 9 pieces of electronic used to supply the 14 high voltages to the 9 x 4 MAPMTs via the EC-HV and EC-dynode boards It should also include switches used to switch different high voltages to the cathode when the incoming light gets too high and could damage the MAPMTs. This is measured by the KIs and the PDM board holding an algorithm in its FPGA commands the switches. It should be located between the ASIC-boards See Philippe Gorodeztky’s talk on HV and switches

23. Risk analysis 23 MAPMTs not available at due time Packaged ASICs yield low Delay in EC assembly/integration Failure in MAPMT pins soldering within the EC EC boards and integration not matching the spec EC insulation insufficient Failure of 1 component (MAPMT, HV supply, HV switch, EC, ASIC…) Development plan built taking these risks into account. Spares available.

24. The development plan 24 Important constraints: compactness, fragile MAPMTs, dense stack of 3 pcbs, 14 different (high) voltages, potting, precise positioning Production of a mechanical mock up of the EC-front – Check the mechanical design of the 3 PCBs of the EC-front – Check the assembly of the EC-front – Check the potting procedures – Development of all the tools needed for the continuation Production of a prototype of the EC unit – Check the PCBs electrically, as well as their performances (individually and together) – Validate the assembly and the potting process Production of the Flight Model EC units – Tests at each step of the fabrication and integration

25. The development plan: tests 25 ElementsCodeType of testsDuration MAPMTAPerformances and uniformityFew hours/unit – 2 weeks total EC-dynodeBElectrical continuityFew minutes/unit – 1 day total EC-anodeCElectrical continuity15 mn/unit – 1 or 2 days total EC-HVDElectrical continuityFew minutes/unit – 1 day total ASICEFunctionalities20 mn/unit – 4 weeks total EC-ASICFPerformances and functionalities1-2 days/unit – 2 weeks total HV-BOXGFunctionalitiesFew hours/unit – 2 weeks total (A + B)HElectrical continuity – assemblyFew minutes/unit – 1 day total (D + G)IElectrical continuity – functionalities - assembly1 hour/unit – 1-2 days total (A + B + C + D)JElectrical continuity – functionalities - assemblyFew hours/unit – 2-3 days total (J + G)KMAMPT powering – consumptionFew hours/unit – 2-3 days total (J + F)LPerformances and functionalities without HVFew hours/unit – 2-3 days total (K + F)MPerformances and functionalities with HV1 day/unit – 2 weeks All the elements will have to be tested individually and associated For some of them, the tests should be simple and fast Two dedicated test boards will be needed: – ASIC (CQFP160) test board  ASIC selection and MAPMT tests – EC-ASIC test board  verification of EC-ASIC functioning and performances

26. The planning (GANT) Feasibility study carried out end of last year Mechanical prototype has to be built as soon as possible in order to validate the assembly and potting of the EC-front. 26

27. The planning (GANT): EC-front EC-front CAD work (bodies, schematic, design) early 2012 Production of few samples of each board (after design review) with the goal being the test of EC unit prototype 27

28. The planning (GANT): EC-back and ASIC ASICs have to be sorted out (good/bad) after packaging and before being soldered on the EC-ASIC boards Proto EC-unit front test will be done when proto of EC- ASIC has been fabricated and tested. 28

29. The planning (GANT) Phase B review takes place at the end of the test of the EC-unit prototype tests. 29 Finished

30. Already done (1/2) EC-dynode schematic 30 Dedicated CAD elements EC-dynode routing

31. Already done (2/2) EC-anode schematic 31 Schematic of test board ASIC (CQFP160 packaged)