1. Development of Pixel Phase 2 chip

2. Goals New Pixel Chip needed to go beyond the Phase 1 baseline chip – Should be the solution for Phase 2 pixel – Should be ready for use at a Layer 1 replacement of Pixel Phase 1 detector This will have to be decided ~2016 – Requests: Improved radiation hardness ~ 1 Grad Improved data rate capability of the ROCs ~ 1 GHz/cm 2 Increased granularity, i.e. smaller pixels~(25-50)x100 um 2 Considering New trigger functionalities: – Selective readout or self-triggering

3. New Pixel Chip Development Baseline technology CMOS 65nm CMS Groups (present) – Torino, FNAL, CERN started – Perugia, Pisa starting – Interest of: Bari, Genova, Lisbona, Padova (via EPIX) Short Timeline – MPW submissions FALL 2013: first submission on analog  TORINO+FNAL (?) – Final prototype for 2017 Sinergies and fundings – EU Initial Training Network (ITN): EPIX -answer in April Financed a total of 40 man years CMS with 12 man years (of which INFN: 9 – R&D collaboration with ATLAS Pixel Torino only INFN covering analog electronics – PRIN 2012: H-TEAM

4. 65nm technology – Frame contract in place ~end March – Defining multi-party NDA agreement Allowing designs to flow between: Foundry Broker CERN Institutes (EU) Institutes (US) – Then Design kit development with VCAD, Digital libraries (with ~1 at layout level) Rad rad memory generator Rad tol tests – New extended test structures back from production – Radiation test program for 1Grad/ 10 16 Neu/cm 2 to be discussed with pixel phase 2 community Test structures can be given to institutes ready/willing to make radiation test 65nm designs – Clic pix has just gotten back a 64x64 array of 25x25um pixel prototype chip (analog + digital). 6 weeks turn-around ! Testing of chip plus test with sensor planned for coming months – High speed serializer prototype System Verilog training at CERN in the planning 4 CERN news/status/plans

5. First attempt to get ATLAS and CMS Phase 2 hybrid pixel Readout ASIC communities to work/talk together – Very similar requirements: Rates, radiation, pixel size, triggering, possible ROI, readout – Using same ASIC technology: 65nm CMOS – Both communities short of chip design resources (manpower and money) – Agrees that it is better to work together where possible/appropriate. 2 day Workshop: – Very good and interesting exchange between the two communities. – We want to have such a workshop again: ~ every year – Potential for common work: Technology and radiation qualification: Very good – Booth communities “worried” about radiation qualification up to 1Grad. Analog: – Pixel front-end: Possible but not obvious – Other blocks (DACs, monitoring ADC, PLL): Possible Digital: – Possibility for common architecture simulation and verification framework Common chips: Common submissions of test chips: Yes – Common final chip: Unlikely but time will show – Investigating option of making R&D collaboration on electronics (ASIC’s) for very high rate pixel detectors: ATLAS, CMS and possibly CLIC EPIX funding will make such a collaboration easier – Agenda: http://indico.cern.ch/conferenceDisplay.py?confId=208595http://indico.cern.ch/conferenceDisplay.py?confId=208595 5 ATLAS – CMS pixel 65nm workshop

6. Forming Groups: – CMS : Torino, Perugia, Pisa, Padova, Fermilab, CERN, PSI – ATLAS: NIKHEF, Bonn, CPPM-Marseille, LBNL, UCSC ATLAS and CMS phase 2 pixel readout ASIC have many communalities: – Hybrid pixel based on 65nm CMOS technology. – High hit rate pixel detector ( ~2GHz/cm 2 ) – High radiation tolerance: 1Grad, 10 16 Neu/cm 2 over 10 years – Pixel size: ~25mm x 100mm – Measurement of deposited charge per pixel with 4 – 8bits resolution. – Use of local pixel regions (2x2 to 4x4) to share logic functions and buffering. – Digital architecture with intelligent pixels cells/regions with data buffering and triggered data extraction. – High-speed serial readout compatible with the use of the second generation radiation hard link from CERN (LPGBT). – On-chip power regulation/conversion to get optimized low mass power distribution system. RD pixel 65 collaboration – Initial endorsement from ATLAS and CMS (on-going) – RD proposal submission to LHCC this spring (encoraged to go along with this) Initial 3 year R&D plan with clear objectives and contributions: – Technology radiation test and qualification – Pixel building blocks – Global architecture design, simulation and verification (tools) – Shared prototype submissions – Open to other communities but 100% driven by ATLAS/CMS phase 2 pixel upgrades !. Not a generic 65nm ASIC or generic pixel collaboration – Strong correlation with EPIX ITN on the 65nm technology. 6 CMS-ATLAS 65nm collaboration

7. An EU Initial Training Network (ITN) proposal coordinated by CERN – Novel high rate pixel detector electronics – 3 pixel technology work-packages: 65nm ASICs, Interconnect and Fast readout  Total manpower requested: ~40 man years – 12 Early Stage Researchers (ESR = ~PHD students) – 2 Experienced Researchers (ER = ~post doc) – CMS: 4, ATLAS: 4, LHCb: 1, ALICE: 1, CLIC: 2, Other Companies: 2, Plus div. Associated partners  High rate radiation hard pixel ICs: 65nm for ATLAS/CMS pixels CERN-CMS: Modelling and optimization of intelligent and fault tolerant very high rate pixel architecture INFN Perugia-CMS: Design and optimization of very low power pixel region logic INFN Torino-CMS: Development of very low power small size analogue electronics for high rate pixels INFN Padova-CMS: Radiation hardness assessment of 65nm technology Bonn-ATLAS: Radiation hard mixed signal chip design in 65nm Nikhef-ATLAS: Radiation hard timing circuits in 65nm CPPM-ATLAS: SEU tolerant memories and registers Associated partners: Perugia, Pisa, MAPRad, LBNL, Fermilab High density and low mass interconnect and packaging CERN–CLIC: High density interconnect for pixel detectors and X-ray imaging CERN–ALICE: Low mass and low cost interconnect solutions for pixel detectors IZM–ATLAS: 3D interconnect for hybrid pixels. Advacam - CLIC: Ultra-fine pitch Cu pillar flip-chip interconnect Associated: Rockwood, Mergenthaler High speed readout and characterization: LHCb + commercial pixel systems: CERN–LHCb: High bandwidth data interface for pixel detectors ASI: Readout and characterization system for pixel detectors imXPAD: Pixel chip simulation, readout and calibration system Associated: Agilent EU funding result in ~April Can be the catalyser to get ATLAS and CMS to work together on phase 2 pixel R&D !. 7 EPIX: Enabling Pixels for Innovative eXperiments

8. Possible Pixel Phase 2 Detector layout Pixel Phase 2 – Layout step 1 = CMS Pixel Phase 1 layout Possible extention to very forward disks

9. Activities on-going CERN: – Interested on Digital architecture / verification – Generic / statistical study done (with E.Conti- PG) – Moving soon to System Verylog Torino: – Working on very front end analog electronics – 65nm TSMC installed – Now working on: fast comparator, ADC, ToT – Schematics, simulation, starting layout, post-layout simulations – Objective: MPW in autumn with full analog FNAL – test structures for rad-hard studies in: 130nm, 65nm – Studying solutions for pre-amplification / shaper stage to be design in 65nm – Interested to make a small chip for R&D sensor studies in 130nm Discussion at next TK Upgrade week Perugia – Installing 65nm, System Verilog

10. Status and prespective Lot of things are starting up – 65nm design more advanced at CERN (2-3 people working on it) Full learning curve at Torino and FNAL – R&D collaboration Most important the rad-hard studies – Advanced tools for chip architecture (digital) Courses of System Verilog – First studies on Trigger contributions On CMS – INFN side – New groups welcome to contribute