1. Report on INFN activities CHIPIX65 - project
L.Demaria on behalf of CHIPIX65 project
L. Demaria - INFN activities of CHIPIX65

2. Challenges for CHIPIX65
Design of innovative electronics in strategic area of INFN, using the “novel” CMOS 65nm technology, with a large participation of INFN community
INFN is one of founding members of RD53, an international collaboration for the R&D phase of an innovative chip for the pixel detector of ATLAS and CMS at HL_LHC, and the goals of RD53 are the main focus of CHIPIX65 milestones:
Small pixels: 50x50um2 (or 25x100um2)
Large chips: >2cm x 2cm ( ~1 billion transistors)
Hit rates: ~2 GHz/cm2
Radiation: 1Grad, 1016 neu/cm2 (unprecedented)
Trigger: 1MHz, 10us (~100x buffering and readout)
Low power - Low mass systems
L. Demaria - INFN activities of CHIPIX65

3. CHIPIX65 Project Same IC-designers + 2 additions
Less for Irrad (also in ScalTech28)
+ IC-designer from DEI
1 PhD student more (IC-designer analog)
1 staff IC-designer digital
Same IC-designers +
2 additions
L. Demaria - INFN activities of CHIPIX65

4. Main work done: First 180 days
Irradiation of basic test structures (Pd)
Design of Very Front End analog electronics (Pv,To)
Work on IP-block
Defining responsibility of IP-block (Ba,Mi,Pd,Pv,Pi,To)
First design of IP-block (Ba,Mi,Pv,Pi)
Digital architecture
Undergoing development of the simulation and verification framework (Pg)
DESIGN activities were assuming TSMC/IMEC/CERN contract ready on spring NDA arrived only 1 week ago to all sites  impact on schedule
NB: prediction of last year were for October-November 2013 (!)
All this will be better shown along this presentation
L. Demaria - INFN activities of CHIPIX65

5. Main 2014 CHIPIX65 contributions to RD53
Radiation WG (Padova):
Irradiation campaign at Legnaro with low energy protons (TDD studies)
foreseen also irradiation with x-ray machine (TID)
Analog WG (Pavia, Torino)
Design of Very Front end chain, low power, low threshold (<1000e-) with synchronous and asynchronous comparators
IP-block WG (Bari, Milano, Pavia, Padova, Pisa, Torino)
16 out of 34 IP-block under INFN responsibility
Simulation WG (Perugia)
Main contributor to the development of the simulation and verification framework
Top Level WG:
Activity is at a preliminary stage. Contribution mainly from LBNL (USA)
IO WG:
Activity will start during the second half of New convener being identified now (Roberto Beccherle – Pisa)
L. Demaria - INFN activities of CHIPIX65

6. RD53 WG1 (Radiation test/qualification): Summary
• CERN test structures (65nm nMOS & pMOS transistors)
CERN: 10-keV X ray (CERN), till 200 Mrad(SiO2)
CPPM: 10-keV X ray (CERN), till 1Grad(SiO2) , 20 & 100 ºC annealing
Padova: 3-MeV proton (Padova), till 1Grad(SiO2), 20 & 100 ºC annealing (31-st March, May 2014)
TSMC test structures - FNAL layout (65 nm nMOS & pMOS transistors)
Fermilab: Co-60 γ ray, -20 ºC irradiation, till 1Grad(SiO2)
Results from Padova
L. Demaria - INFN activities of CHIPIX65

7. Digital Pixel architecture
Perugia
Goal: Simulation and optimization of pixel chip architectures to be implemented in prospective next generation pixel readout chips.
VEPIX53: a flexible Verification Environment for PIXel chips in RD53 in SystemVerilog + UVM (collaboration with RD53, ).
DUT: behavioral, time-based description of a simple pixel chip with basic functionality (conversion of hits into discriminator outputs, computation of hit time of arrival and amplitude, trigger selection, column arbitration).
UVM verification components connected to interfaces defined in DUT:
hit generation (different classes of typical detector hits can be generated)
monitoring of pixel chip input and output
conformity checks and statistics collection.

8. Design of Analog VFE @ Torino
Baseline Solution: Single stage front end with CSA + Discriminator (synch discr.)
Low power: 5uW/pixel cell (or below)
(FEI4~15uW/pix analog, PSI46~6.7uW analog [RH])
Low noise: 90e- for Cd~100 fF (or below)
7 sigma=560e-; threshold max 1000e-
FAST ToT: 30ke- signal max into max 250nsec
others 400ns for 10 or 30ke-
High resolution of Digital information: 8 bits (lower resolution possible)
FEI4: 4 bits to stay in 400ns (40 MHz clock)
NO-threshold trimming via DAC
Hardware solution (corrections stored in capacitors): Never done before in pixel VFE
Dimensions: max area ~25x50 um2
Layout dimensions: 26x35 um2
L. Demaria - INFN activities of CHIPIX65

9. VFE Performance (Torino)
128
ENC e-
#ADC counts
100 fF
for 250ns ToT
512 MHz 50
256 MHz 50
128 MHz 50
100 10
Cdet fF
Q (Ke-)
LINEARITY ot DIGITIZED ToT
(here shown up to 8 bits in 250ns
Noise vs Detector Capacitance
L. Demaria - INFN activities of CHIPIX65

10. PAVIA
L. Demaria - INFN activities of CHIPIX65

11. IP Block for RD53
Out of 34 IP-block identified in RD53, INFN has proposed to contribute at ~16 of them:
as main organizer (11)
as participant (5)
In the following few slides on first prototypes ready for submission in fall 2014 (design in 65nm already present):
ADC
Band-Gap
SLVS driver
SRAM
Serialiser-deserialiser
others IP-blocks could be ready for end of year
L. Demaria - INFN activities of CHIPIX65

12. Bari IP-block
Progettazione di un convertitore digitale-analogico (DAC) a 10 bit per la polarizzazione dell’elettronica di front-end
1o prototipo da sottomettere a Ottobre 2014
Collaudo agli inizi del 2015
Implementazione di eventuali modifiche e nuova sottomissione nel 2015
Progettazione di un convertitore analogico-digitale (ADC) a 12 bit per il monitoring dei parametri funzionali del chip
Sottomissione 1o prototipo: Q1 2015
Collaudo: Q2-Q3 2015
Implementazione di eventuali modifiche e nuova sottomissione: Q3/Q
Sviluppo di soft-IP per il controllo remoto del chip, adottando tecniche di ridondanza per aumentare la resistenza ai Single Event Upset: Q – Q1 2015
L. Demaria - INFN activities of CHIPIX65

13. IP-block (Mi) DICE RAM Cell
Interest of Milano (in CHIPIX65, applying for RD53) to develop radiation hard SRAM
array of 256x256 DICE (Dual Interlocked storage Cell) RAM cells almost ready for integration. It comes from a work done in AIDA. Size of about 1.8x3.3 um2
Other two designs more radiation hard almost ready
This could be used either in the PUC or in the EOC
SEU recovery in ~20ns
Schematics
Layout V.1
L. Demaria - INFN activities of CHIPIX65

14. PAVIA
L. Demaria - INFN activities of CHIPIX65

15. PLL/SER/CDR  data IO & clock management
ORGANIZATION on-going
L. Demaria - INFN activities of CHIPIX65

16. IP-cores for high speed links PISA
Standard Cell based SER/DES in CMOS 65nm
Ready for the CHIPIX65 submission in fall 2014
RTL preliminary synthesis completed
2GHz
Worst                1.4 mW
Best                  1.6 mW
Worst                6.0 mW
Best                8.3 mW
Collaboration with UCSB on high speed TX & RX differential PADs
Foreseen for end of year. Needs NDA
L. Demaria - INFN activities of CHIPIX65

17. Padova IP-Block PLL VCO : specs to be better defined.
L. Demaria - INFN activities of CHIPIX65

18. CHIPIX submissions
IP-block submission (2 blocks of 2x2 mm2)- October 2014:
SLVDS (Pavia)
Band-Gap (Pavia, Milano)
SRAM (Milano)
DAC (Bari)
Serialiser/deserialiser (Pi)
Analog Very Front End submission (1 block of 2x2 mm2)- October 2014
Synchronous, Auto-zeroing, FAST ToT analog front end (Torino)
Asynchronous analog front end (Pavia)
Analog readout: max (12x12) pixels + Matrix: (12x32) pixel
In the pipeline
Next IP blocks to be ready :
ADC (Bari), TX-RX (Pisa), Digital Logic RAdHard (Milano), PLL (?)
Pixel-Matrix with complex synthetized digital logic (pixel and readout) [Torino, Pisa, Pavia, Milano]
L. Demaria - INFN activities of CHIPIX65

19. October submission: IP-block
Esercizio di floorplanning che
Indica che far stare tutto su di
un solo IP-block, e’ difficile e presenta svantaggi.
Bandgap:
includere versioni CERN, CPPM per confronto
DAC:
Includere anche disegno DAC in tensione di Praga
SRAM:
Milano abbisogna di piu’ spazio se possibile (256x256 invece di 128x256 celle)
L. Demaria - INFN activities of CHIPIX65

20. October submission – VFE block
1) One core AREA with ANALOG testing for ASYNC design(PAVIA)
2) One core AREA with ANALOG testing of SYNC design (Torino)
3) One core AREA with simple digital readout and measurement of ToT (slow and fast ToT) 1 3 2
L. Demaria - INFN activities of CHIPIX65

21. Simulazione, 5 eventi singolo pixel in vari casi, si vede bene il clock del ToT e il caso di timeout nel conteggio del ToT
CHIPIX65
L. Demaria - INFN activities of CHIPIX65

22. I/O group Responsabile R. Beccherle
1) I/O: Evaluation and definition of I/O protocols supporting 2Gbps or higher serial links, command based triggering up to 1MHz rate and minimum dead-time.
- 80Mbps or higher serial input, with command decoder to configure and operate the chip. Evaluation of a slow control protocol.
Command and Clock should be encoded on a single line.
- 2Gbps Serial Output links will require to evaluate different output data formats and compression alternatives.
- A duplex solution where all I/O takes place on a single serial connection should be considered. Investigation of link redundancy schemes to be eventually used on less data demanding layers.
2) Interfaces: Evaluation of compatibility with defined interfaces such as LPGBT.
3) IP blocks related to I/O: interface driver, clock recovery, clock multiplier methods, LVDS driver and receivers. [Work to be shared with the IP group]
4) Off chip connectivity: Calculation, Simulation and Test of transmission performance with realistic interconnects. I/O should not stop at the chip pads but extend to the system immediately outside the chip. High speed cables and protocols and even test interfaces. Therefore we should develop a specification for the system around it and a test setup.
L. Demaria - INFN activities of CHIPIX65

23. Main Milestones for 2015 Test of first IP-blocks 1-4-2015
Measurement of SEU rate with SRAM
Test of small pixel array
Definition of Very Front End analog architectures
Test of all IP-block prototypes
L. Demaria - INFN activities of CHIPIX65

24. Conclusions Good starting of the CHIPIX65 project
Layout in TSMC 65nm in 5 out of 6 sites. With CERN/TSMC contract approved, from September all groups will be capable of working with TSMC 65nm
Work on IP-block and VFE-analog going very well
For 2015 INFN will focus more on adding complex digital architecture in a small pixel array / matrix of about 3x4 mm2
L. Demaria - INFN activities of CHIPIX65