Technical University Tallinn, ESTONIA 1 Raimund Ubar Tallinn Technical University Estonia Stockholm, May 19, 2003 Testing.

Technical University Tallinn, ESTONIA 1 Raimund Ubar Tallinn Technical University Estonia raiub@pld.ttu.ee www.ttu.ee/ˇraiub/ Stockholm, May 19, 2003 Testing Strategies for NoC

Technical University Tallinn, ESTONIA 2 OUTLINE Introduction: how much to test? Defect modeling Hierarchical approaches to test generation Built-in self-test Stimuli generation in BIST Response compaction and signature analyzers BIST architectures Hybrid BIST P1500 Standard for SoC and NoC testing Testing the communication infrastructure Conclusions

Technical University Tallinn, ESTONIA 3 Introduction The reliability of electronic systems is no longer a topic of limited critical applications like –military, aerospace and nuclear industries, where –failures may have catastrophic consequences Electronic systems are becoming ubiquitous –their reliability issues are present in all types of consumer applications Adequate testing of electronic products is a must

Technical University Tallinn, ESTONIA 4 Introduction The complexity of systems, new failure models and modern technologies –cause the necessity for developing more efficient test methods In the middle of 1990s, the core based SoC concept evolved –new strategies and standards dedicated to SoC test Today the design methdology is moving towards the NoC approach –the presence of the regular communication structure requires new dedicated methods to test it

Technical University Tallinn, ESTONIA 5 Introduction Dependability Fault-Tolerance Fault Diagnosis BIST Test Reliability Security Safety There is no sequrity on the earth, there is only oportunity Douglas McArthur (General) Test Diagnosis Design for testability:

Technical University Tallinn, ESTONIA 6 Introduction – Test Tools Test System Fault table System model Test generation Fault simulation Test result Fault diagnosis Go/No go Located defect Test experiment Test tools

Technical University Tallinn, ESTONIA 7 Introduction – Test Tasks Fault Diagnosis and Test Generation as direct and reverse mathematical tasks: dy = F(x 1,..., x n )  F(x 1  dx 1,..., x n  dx n ) dy = F(X, dX) Direct task: Test generation: dX, dy = 1 given, X = ? Reverse task: Fault diagnosis: X, dy given, dX = ? Fault simulation: X, dy = 1 given, dx k = ? Fault Simulation is a special case of fault diagnosis

Technical University Tallinn, ESTONIA 8 Introduction – Fault Diagnosis 0110 T 6 0010011 FaultF 5 located FaultsF 1 andF 4 are not distinguishable Fault localization by fault tables No match, diagnosis not possible

Technical University Tallinn, ESTONIA 9 Test as the Quality Problem Quality policy Yield (Y) P,n Defect level Design for testability Testing P - probability of a defect n - number of defects - probability of producing a good product

Technical University Tallinn, ESTONIA 10 How Much to Test? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams

Technical University Tallinn, ESTONIA 11 How Much to Test? Paradox: 2 64 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 2 65 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Time can be your best friend or your worst enemy (Ray Charles) & & x1x1 x2x2 x3x3 y State q Y = F(x 1, x 2, x 3,q) * 1 1 Y = F(x 1, x 2, x 3 ) Bridging fault 0

Technical University Tallinn, ESTONIA 12 How to Generate a Good Test? Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates

Technical University Tallinn, ESTONIA 13 Complexity vs. Quality Problems: Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies How to improve test quality at increasing complexities of today's systems? Two main trends: –Defect-oriented test and –High-level modelling Both trends are caused by the increasing complexities of systems based on deep-submicron technologies

Technical University Tallinn, ESTONIA 14 Towards Solutions The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels –But this moves us even more away from the real life of defects (!) To handle defects in circuits implemented in deep-submicron technologies, new defect-oriented fault models and defect- oriented test methods should be used –But, this is increasing even more the complexity (!) As a promising compromise and solution is: To combine hierarchical approach with defect orientation

Technical University Tallinn, ESTONIA 15 OUTLINE Introduction: how much to test? Defect modeling Hierarchical approaches to test generation Built-in self-test Stimuli generation in BIST Response compaction and signature analyzers BIST architectures Hybrid BIST P1500 Standard for SoC and NoC testing Testing the communication infrastructure

Technical University Tallinn, ESTONIA 16 Fault and defect modeling Defects, errors and faults An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults - defects Physical faults do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with fault models System Component Defect Error Fault

Technical University Tallinn, ESTONIA 17 Transistor Level Defects Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

Technical University Tallinn, ESTONIA 18 Mapping Transistor Defects to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Generic function with defect: Function: Faulty function: A transistor fault causes a change in a logic function not representable by SAF model Defect variable: d =d = 0 – defect d is missing 1 – defect d is present Mapping the physical defect onto the logic level by solving the equation:

Technical University Tallinn, ESTONIA 19 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

Technical University Tallinn, ESTONIA 20 Why Boolean Derivatives? Distinguishing function: Given: BD-based approach: Using the properties of BDs, the procedure of solving the equation becomes easier

Technical University Tallinn, ESTONIA 21 Functional Fault vs. Stuck-at Fault No Full SAF-TestTest for the defect x1x1 x2x2 x3x3 x4x4 x5x5 x1x1 x2x2 X3X3 x4x4 x5x5 1 1110-10-01 2 0--111-001 3 0110101110 4 10110 5 1100- Full 100% Stuck-at-Fault-Test is not able to detect the short: The full SAF test is not covering any of the patterns able to detect the given transistor defect  Functional fault

Technical University Tallinn, ESTONIA 22 Defect coverage for 100% Stuck-at Test Results: the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1) the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

Technical University Tallinn, ESTONIA 23 Generalization: Functional Fault Model Constraints calculation: y Component F(x 1,x 2,…,x n ) Defect WdWd Component with defect: Logical constraints Fault-free Faulty Fault model: (dy,W d ), (dy,{W k d }) Constraints: d = 1, if the defect is present

Technical University Tallinn, ESTONIA 24 Functional Fault Model for Stuck-ON Stuck-on x1x1 x2x2 Y V DD V SS x1x1 x2x2 NOR gate Conducting path for “10” RNRN RPRP x1x1 x2x2 yydyd 0011 0100 100Z: V Y /I DDQ 1100 Condition of the fault potential detecting:

Technical University Tallinn, ESTONIA 25 Functional Fault Model for Stuck-Open Stuck-off (open) x1x1 x2x2 Y V DD V SS x2x2 NOR gate No conducting path from V DD to V SS for “10” x1x1 Test sequence is needed: 00,10 x1x1 x2x2 yydyd 0011 0100 100Y’ 1100 t x 1 x 2 y 1 0 0 1 2 1 0 1

Technical University Tallinn, ESTONIA 26 Functional Fault Model for Shorts Example: Bridging fault between leads x k and x l The condition means that in order to detect the short between leads x k and x l on the lead x k we have to assign to x k the value 1 and to x l the value 0. xkxk xlxl x* k d Wired-AND model x k *= f(x k,x l,d)

Technical University Tallinn, ESTONIA 27 Functional Fault Model for Sequential Shorts Example: x1x1 x2x2 x3x3 y & & x1x1 x2x2 x3x3 y & & & Equivalent faulty circuit: Bridging fault causes a feedback loop: Sequential constraints: A short between leads x k and x l changes the combinational circuit into sequential one t x 1 x 2 x 3 y 1 0 2 1 1 1 1

Technical University Tallinn, ESTONIA 28 First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System Component Low level k WFkWFk WSkWSk Environment Bridging fault Mapping High level

Technical University Tallinn, ESTONIA 29 Faults and Test Generation Hierarchy Circuit Module System Network of gates Gat e Functional approach F ki Test F k W F ki W S F Test W F k W S k Structural approach Network of modules W d ki Interpretation of W F k : - as a test on the lower level - as a functional fault on the higher level Higher Level Component Lower level k WFkWFk WSkWSk Environment Bridging fault

Technical University Tallinn, ESTONIA 31 Hierarchical Test Generation In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes These modes will usually contain: –a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or –a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path The I-paths and F-paths constitute connections that can be used to propagate test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) In the hierarchical approach, top-down and bottom-up strategies can be distinguished

Technical University Tallinn, ESTONIA 32 Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c Local test: A = a.x B = f’(D) C = c.x a,c,D fixed x - free a System Module c

Technical University Tallinn, ESTONIA 33 Hierarchical Test Generation Approaches Top-down approach - to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible, since it does not narrow the search for the global test solution to pregenerated patterns for the system modules The method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’.x d’.x c’.x Symbolic global test: A = a’.x D’ = d’.x C = c’.x a’ c’ a’,c’,D’ fixed x - free System Module

Technical University Tallinn, ESTONIA 34 Basics of Theory for Test and Diagnostics Two basic tasks: 1. Which test patterns are needed to detect a fault (or all faults) 2. Which faults are detected by a given test (or by all tests) ALU & 1 0 0 & 1 0 Gate Multiplier System Boolean differential algebra only for logic level Decision Diagrams for logic and higher levels

Technical University Tallinn, ESTONIA 35 Two trends: high-level modeling –to cope with complexity low-level modeling –to cope with physical defects, to reach higher acuracy Hierarchical Diagnostic Modeling Boolean differential algebra BDD-s High-Level DD-s

Technical University Tallinn, ESTONIA 36 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: 0 1 1 0 1 0 0 Boolean derivative and test generation: 1 0 Functional BDD

Technical University Tallinn, ESTONIA 37 Low-Level Test Generation on SSBDDs Test generation for a bridging fault: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 x7x7 Network Defect WdWd 2. Activate a path: Bridge between leads 7 3 and 6: (dx 7,W d ) 6 7373 1 2 5 7272 7171 y 0 1 Path to 7 1 : x 1 = 1, x 2 = 1 Path from 7 1 : x 5 = 0 W d : x 6 = 0, x 7 = 1 1. Solve the constraint: Test pattern: 1 2 3 4 5 6 7 y 1 1 0 0 1 1

Technical University Tallinn, ESTONIA 38 Test Generation on High Level DDs R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program:

Technical University Tallinn, ESTONIA 39 Hierarchical Test Generation on DDs R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram Hierarhical test generation with DDs: Scanning test Control: y 1 y 2 y 3 y 4 = x032 Data: For all specified pairs of (R 1, R 2 ) Test program: Low level test data

Technical University Tallinn, ESTONIA 40 Test Generation for RTL Cores y 3  0 CR’ 2 C y 2 A 2R’ 2 y 1 R’ 1 3 B F(B,R’ 3 ) A A A  R’ 1  0  0  0 2 Y,R 3 R 2 0 1 1 0 0 2 3 R 1 C R’ 1 1  1 0 0 1 0 2 0 1 0 1 1 C+R’ 2 R’ 3 2 1 Transparency functions on Decision Diagrams: Y = C  y 3 = 2, R 3 ’ = 0 C - to be tested R 1 = B  y 1 = 2, R 3 ’ = 0 R 1 - to be justified + R 3 R 2  F R 1 A B C Y y 2 A y 3 y 1 s High-level path activation on DDs 0 2

Technical University Tallinn, ESTONIA 41 Test Generation for RTL Cores Symbolic test sequence: y 3 =2 R’ 2 =0 y 2  0 R 3 =D A  R’ 1 A =D 1 R’ 1 =D 2 B 2 R’ 3 =0 y 1 =2=2 y 3  0 C =D q’=4 Fault manifestation q’=2q’=1q’=0 R’ 2 = 0 y 2 q’=1 q’=2 Constraints justification Fault propagation t t-1t-2t-3Time:  0 High-level test generation example:

Technical University Tallinn, ESTONIA 42 Test Generation for Processor Cores I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

Technical University Tallinn, ESTONIA 43 Test Generation for Processor Cores High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

Technical University Tallinn, ESTONIA 44 Test Generation for Processor Cores IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

Technical University Tallinn, ESTONIA 45 Test Generation for Processor Cores IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 I IN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

Technical University Tallinn, ESTONIA 46 DECIDER: Hierarchical ATPG R 2 M 3 e + M 1 a * M 2 b   R 1 IN    c d y 1 y 2 y 3 y 4 y 4 y 3 y 1 R 1 +R 2 + R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Modules or subcircuits are represented as word-level DD structures Logic Synthesis Scripts Design Compiler (Synopsys Inc.) Gate Level Descriptions SSBDD Synthesis SSBDD Models of FUs Hierarchical ATPG RTL Model (VHDL) FU Library (VHDL) FU Library (DDs) RTL DD Synthesis Test patterns RTL DD Model

Technical University Tallinn, ESTONIA 47 ATPG: Experimental Results Reference ATPGs: HITEC - T.M. Nierman, J.H. Patel, EDAC, 1991 GATEST - E.M.Rudnick et al., DAC, 1994 TTU: DET/RAND - hierarchical deterministic- random ATPG GENETIC - gate-level ATPG based on genetic algorithms

Technical University Tallinn, ESTONIA 49 Built-In Self-Test Motivations for BIST: –Need for a cost-efficient testing –Doubts about the stuck-at fault model –Increasing difficulties with TPG (Test Pattern Generation) –Growing volume of test pattern data –Cost of ATE (Automatic Test Equipment) –Test application time –Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: –Additional pins and silicon area needed –Decreased reliability due to increased silicon area –Performance impact due to additional circuitry –Additional design time and cost

Technical University Tallinn, ESTONIA 50 BIST Techniques BIST techniques are classified: –on-line BIST - includes concurrent and nonconcurrent techniques –off-line BIST - includes functional and structural approaches On-line BIST - testing occurs during normal functional operation –Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used –Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by executing diagnostic software or firmware routines Off-line BIST - system is not in its normal working mode, usually –on-chip test generators and output response analyzers or microdiagnostic routines –Functional off-line BIST is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models –Structural off-line BIST is based on the structure of the CUT and uses structural fault models (e.g. SAF)

Technical University Tallinn, ESTONIA 51 Built-In Self-Test System-on-Chip testing Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution –need for external ATE Combined solution –mostly on-chip, ATE needed for control On-chip solution –BIST

Technical University Tallinn, ESTONIA 52 Built-In Self-Test Embedded tester for testing multiple cores

Technical University Tallinn, ESTONIA 53 Built-In Self-Test BIST components: –Test pattern generator (TPG) –Test response analyzer (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) Two widespread schemes: –test-per-scan –test-per-clock

Technical University Tallinn, ESTONIA 55 LFSR: Pseudorandom Test Generation Using special LFSR registers Several proposals: –BILBO –CSTP Main characteristics of LFSR: –polynomial –initial state –test length

Technical University Tallinn, ESTONIA 56 Pseudorandom Test Generation LFSR – Linear Feedback Shift Register: 1xx2x2 x3x3 x4x4 x2x2 x 1 x4x4 x3x3 Polynomial: P(x) = 1 + x 3 + x 4 Standard LFSR Modular LFSR

Technical University Tallinn, ESTONIA 57 Pseudorandom Test Length Problems: Very long test application time Low fault coverage Area overhead Additional delay Possible solutions Combining pseudorandom test with deterministic test –Multiple seed –Bit flipping Hybrid BIST The main motivations of using random patterns are: - low generation cost - high initial efeciency

Technical University Tallinn, ESTONIA 58 BIST: Weighted pseudorandom test Hardware implementation of weight generator LFSR && & MUX Weight select Desired weighted value Scan-IN 1/2 1/41/8 1/16

Technical University Tallinn, ESTONIA 60 BIST: Response Compression 1. Parity checking UUT Test T riri P i-1 2. One counting UUT Test riri Counter 3. Zero counting

Technical University Tallinn, ESTONIA 61 Signature Analyser 1xx2x2 x3x3 x4x4 x2x2 x 1 x4x4 x3x3 Polynomial: P(x) = 1 + x 3 + x 4 Standard LFSR Modular LFSR UUT Response string Response in compacted by LFSR The content of LFSR after test is called signature

Technical University Tallinn, ESTONIA 62 Signature Analysis In signature testing we mean the use of CRC encoding as the data compressor G(x) and the use of the remainder R(x) as the signature of the test response string P(x) from the UUT Signature is the CRC code word Example: 1 0 1 = Q(x) = x 2 + 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 = R(x) = x 3 + x 2 + 1 P(x) G(x) Signature

Technical University Tallinn, ESTONIA 63 Signature Analysis 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 = R(x) = x 3 + x 2 + 1 P(x) G(x) Signature The division process can be mechanized using LFSR The divisor polynomial G(x) is defined by the feedback connections Shift creates x 5 which is replaced by x 5 = x 3 + x + 1 x0x0 x1x1 x2x2 x3x3 x4x4 IN IN: 01 010001 Shifted into LFSR x5x5

Technical University Tallinn, ESTONIA 64 Signature Analysis Aliasing: UUT Response SA L N L - test length N - number of stages in Signature Analyzer All possible responses All possible signatures Faulty response Correct response N << L

Technical University Tallinn, ESTONIA 65 Signature Analysis Aliasing: UUT Response SA L N L - test length N - number of stages in Signature Analyzer - number of different possible responses No aliasing is possible for those strings with L - N leading zeros since they are represented by polynomials of degree N - 1 that are not divisible by characteristic polynomial of LFSR. There are such strings Probability of aliasing:

Technical University Tallinn, ESTONIA 66 LFSR: Signature Analyser 1 xx2x2 x3x3 x4x4 LFSR UUT Response string for Signature Analysis Test Pattern (when generating tests) Signature (when analyzing test responses) FF

Technical University Tallinn, ESTONIA 67 LFSR: Signature Analyser x2x2 x 1 x4x4 x3x3 Parallel Signature Analyzer: UUT x2x2 x 1 x4x4 x3x3

Technical University Tallinn, ESTONIA 68 Signature Analysis Signature calculating for multiple outputs: LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer Multiplexer LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer Multiplexer

Technical University Tallinn, ESTONIA 70 BIST Components BIST components: –Test pattern generator (TPG) –Test response analyzer (TRA) –BIST controller A part of a system (hardcore) must be operational to execute a self-test At minimum the hardcore usually includes power, ground, and clock circuitry Hardcore should be tested by –external test equipment or –it should be designed self- testable by using various forms of redundancy General Architecture of BIST

Technical University Tallinn, ESTONIA 71 BIST: Test per Scan Assumes existing scan architecture Drawback: –Long test application time Initial test set: T1: 1100 T2: 1010 T3: 0101 T4: 1001 Test application: 1100 T 1010 T 0101T 1001 T Number of clocks = 4 x 4 + 4 = 20

Technical University Tallinn, ESTONIA 72 BIST: Test per Clock Initial test set: T1: 1100 T2: 1010 T3: 0101 T4: 1001 Test application: 1 10 0 1 0 1 0 01 01 1001 T 1 T 4 T 3 T 2 Number of clocks = 8 Combinational Circuit Under Test Scan-Path Register

Technical University Tallinn, ESTONIA 73 BIST Architectures Test per Clock: BILBO - Built- In Logic Block Observer: CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator Combinational circuit LFSR - Signature analyzer LFSR - Test Pattern Generator & Signature analyser Combinational circuit

Technical University Tallinn, ESTONIA 74 BILBO Working modes: B1 B2 0 0Reset 0 1 Normal mode 1 0 Scan mode 1 1 Test mode Testing modes: CC1: LFSR 1 - TPG LFSR 2 - SA CC2:LFSR 2 - TPG LFSR 1 - SA LFSR 1 CC1 LFSR 2 CC2 B1 B2 B1 B2

Technical University Tallinn, ESTONIA 75 Circular Self-Test Circuit Under Test FF

Technical University Tallinn, ESTONIA 76 Circular Self-Test Path CSTP CC R R

Technical University Tallinn, ESTONIA 77 BIST Architectures Test Pattern Generator MISR R1 CC1... STUMPS: Self-Testing Unit Using MISR and Parallel Shift Register Sequence Generator LOCST: LSSD On-Chip Self-Test Rn CCn Error Test Controller SISO TPGSA CUT BS Scan Path

Technical University Tallinn, ESTONIA 79 Store-and-Generate test architecture ROM contains test patterns for hard-to-test faults Each pattern P k in ROM serves as an initial state of the LFSR for test pattern generation (TPG) Counter 1 counts the number of pseudorandom patterns generated starting from P k After finishing the cycle for Counter 2 is incremented for reading the next pattern P k+1 ROMTPGUUT ADR Counter 2Counter 1 RD CL

Technical University Tallinn, ESTONIA 80 Hybrid Built-In Self-Test Hybrid test set contains a limited number of pseudorandom and deterministic vectors Pseudorandom test vectors can be generated either by hardware or by software Pseudorandom test is improved by a stored test set which is specially generated to shorten the on-line pseudorandom test cycle and to target the random resistant faults The problem is to find a trade-off between the on-line generated pseudorandom test and the stored test

Technical University Tallinn, ESTONIA 81 Optimization of Hybrid BIST Cost curves for BIST: Total Cost C TOTAL C Cost of pseudorandom test patterns C GEN Number of remaining faults after applying k pseudorandom test patterns r NOT (k) Cost of stored test C MEM L L OPT

Technical University Tallinn, ESTONIA 82 Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores

Technical University Tallinn, ESTONIA 83 Hybrid BIST for Multiple Cores

Technical University Tallinn, ESTONIA 84 Multi-Core Hybrid BIST Optimization Cost functions for HBIST:Iterative optimization:

Technical University Tallinn, ESTONIA 85 Optimized Multi-Core Hybrid BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially

Technical University Tallinn, ESTONIA 86 Software Based BIST To reduce the hardware overhead cost in the BIST applications the hardware LFSR can be replaced by software, which is especially attractive to test SoCs, because of the availability of computing resources directly in the system (a typical SoC usually contains at least one processor core) Software based test generation: The TPG software is the same for all cores and is stored as a single copy All characteristics of the LFSR are specific to each core and stored in the ROM They will be loaded upon request. For each additional core, only the BIST characteristics for this core have to be stored

Technical University Tallinn, ESTONIA 87 Functional Self-Test Traditional BIST solutions use special hardware for pattern generation on chip, this may introduce area overhead and performance degradation New methods have been proposed which exploit specific functional units like arithmetic blocks or processor cores for on-chip test generation It has been shown that adders can be used as test generators for pseudorandom and deterministic patterns Today, there is no general method how to use arbitrary functional units for built-in test generation

Technical University Tallinn, ESTONIA 88 Broadcasting Test Patterns in BIST Concept of test pattern sharing via novel scan structure – to reduce the test application time:... CUT 1 CUT 2... CUT 1 CUT 2 Traditional single scan design Broadcast test architecture While one module is tested by its test patterns, the same test patterns can be applied simultaneously to other modules in the manner of pseudorandom testing

Technical University Tallinn, ESTONIA 89 Broadcasting Test Patterns in BIST Examples of connection possibilities in Broadcasting BIST: CUT 1 CUT 2 CUT 1 CUT 2 j-to-j connections Random connections

Technical University Tallinn, ESTONIA 90 Broadcasting Test Patterns in BIST... CUT 1 CUT n Scan configurations in Broadcasting BIST:... MISR Scan-In Scan-Out... CUT 1 CUT n MISR 1 Scan-In Scan-Out... MISR n Common MISR Individual and multiple MISRs

Technical University Tallinn, ESTONIA 92 IEEE P1500 standard for core test The following components are generally required to test embedded cores –Source for application of test stimuli and a sink for observing the responces –Test Access Mechanisms (TAM) to move the test data from the source to the core inputs and from the core outputs to the sink –Wrapper around the embedded core

Technical University Tallinn, ESTONIA 93 IEEE P1500 standard for core test The two most important components of the P1500 standard are –Core test language (CTL) and –Scalable core test architecture Core Test Language –The purpose of it is to standardize the core test knowledge transfer –The CTL file of a core must be supplied by the core provider –This file contains information on how to instanciate a wrapper, map core ports to wrapper ports, and reuse core test data

Technical University Tallinn, ESTONIA 94 IEEE P1500 standard for core test Core test architecture It standardizes only the wrapper and the interface between the wrapper and TAM, called Wrapper Interface Port or (WIP) The P1500 TAM interface and wrapper can be viewed as an extension to IEEE Std. 1149.1, since –the 1149.1 TAP controller is a P1500-compliant TAM interface, –and the boundary-scan register is a P1500-compliant wrapper Wrapper contains –an instruction register (WIR), –a wrapper boundary register consisting of wrapper cells, –a bypass register and some additional logic. Wrapper has to allow normal functional operation of the core plus it has to include a 1-bit serial TAM. In addition to the serial test access, parallel TAMs may be used.

Technical University Tallinn, ESTONIA 95 IEEE P1500 standard for core test

Technical University Tallinn, ESTONIA 96 Testing the Communication Infrastructure Consider a mesh-like topology of NoC consisting of –switches (routers), –wire connections between them and –slots for SoC resources, also referred to as tiles. Other types of topological architectures, e.g. honeycomb and torus may be implemented and their choice depends on the constraints for low-power, area, speed, testability The resource can be a processor, memory, ASIC core etc. The network switch contains buffers, or queues, for the incoming data and the selection logic to determine the output direction, where the data is passed (upward, downward, leftward and rightward neighbours)

Technical University Tallinn, ESTONIA 97 Testing the Communication Infrastructure Useful knowledge for testing NoC network structures can be obtained from the interconnect testing of other regular topological structures The test of wires and switches is to some extent analogous to testing of interconnects of an FPGA a switch in a mesh-like communication structure can be tested by using only three different configurations

Technical University Tallinn, ESTONIA 98 Testing the Communication Infrastructure Arbitrary short and open in an n-bit bus can be tested by log 2 (n) test patterns When testing the NoC interconnects we can regard different paths through the interconnect structures as one single concatenated bus Assuming we have a NoC, whose mesh consists of m x m switches, we can view the test paths through the matrix as a wide bus of 2mn wires Concatenated bus concept

Technical University Tallinn, ESTONIA 99 Testing the Communication Infrastructure The stuck-at-0 and stuck-at-1 faults are modeled as shorts to Vdd and ground Thus we need two extra wires, which makes the total bitwidth of the bus 2mn + 2 wires. From the above facts we can find that 3[log 2 (2mn+2)] test patterns are needed in order to test the switches and the wiring in the NoC Concatenated bus concept

Technical University Tallinn, ESTONIA 100 Testing the Communication Infrastructure 0 1 2 3 4 5 6 7 Bus 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 TestDetected faults Stuck-at-1 Stuck-at-0 All opens and shorts 6 wires tested 3[log 2 (2mn+2)] test patterns needed

Technical University Tallinn, ESTONIA 101 Conclusions Defect-oriented and hierarchical test generation approaches as promising trends in the deep-submicron era were discussed Due to the fact that BIST allows at-speed testing and simplifies test access to embedded cores, it has become a popular technique for testing the cores in SoC With properly designed BIST, the cost of added test HW will be more than balanced by the benefits in terms of –Reliability, and –Reduced maintenance cost Useful knowledge for testing NoC network structures can be obtained from the interconnect testing of other regular topological structures

Technical University Tallinn, ESTONIA 102 Conclusions of our Research Experience Who is a test engineer ? The test engineer is the man who is able to program a broken computer

Technical University Tallinn, ESTONIA 1 Raimund Ubar Tallinn Technical University Estonia Stockholm, May 19, 2003 Testing.

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Technical University Tallinn, ESTONIA 1 Raimund Ubar Tallinn Technical University Estonia Stockholm, May 19, 2003 Testing.

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