1. PentiumPro 450GX Chipset Synthesis Steen Larsen Presentation 1 for ECE572 Nov 10 2003

2. General Motive Investigate processor-memory compression methods in a “current” (Intel pipelined FSB and DIMM) architecture to further evaluate advantages of using memory compression architectures. Investigate processor-memory compression methods in a “current” (Intel pipelined FSB and DIMM) architecture to further evaluate advantages of using memory compression architectures. Quickly evaluate using FPGA synthesis different methods of address, instruction, and data compression by modifying and existing production chipset. Quickly evaluate using FPGA synthesis different methods of address, instruction, and data compression by modifying and existing production chipset.

3. What is memory compression? Processor reads and writes to main memory in 32 byte cache lines. Processor reads and writes to main memory in 32 byte cache lines. Optimize this path of information (instruction/address/data) Optimize this path of information (instruction/address/data) Currently simulations, and one implementation at IBM on instruction compression. Currently simulations, and one implementation at IBM on instruction compression. Example of many reads per write Example of many reads per write Example of predominance of “0” and “1” Example of predominance of “0” and “1” Benefit of 1-2% improvement Benefit of 1-2% improvement

4. More detail of 450GX DC/DP

5. Why synthesis to FPGA? Quick re-synthesis and adjustment to existing VHDL structures (reduce simulation and validation cycles) Quick re-synthesis and adjustment to existing VHDL structures (reduce simulation and validation cycles) Rapid advancement of FPGA logic and internal components. (Moore’s law on older chipset) Rapid advancement of FPGA logic and internal components. (Moore’s law on older chipset)

6. Altera Cyclone device Similar to other Altera and Xilinx devices. (LE, PLL, memory, IO, licensed IP) Similar to other Altera and Xilinx devices. (LE, PLL, memory, IO, licensed IP)

7. Altera LE internals

8. Orion 450GX details Focusing only on memory interface Focusing only on memory interface NEC ASIC written in VHDL NEC ASIC written in VHDL PLL, Dual port RAM PLL, Dual port RAM 66MHz 64bit data bus 66MHz 64bit data bus 1 st generation DIMM, ECC 1 st generation DIMM, ECC DC is 208 PQFP and DP is 240 PQFP DC is 208 PQFP and DP is 240 PQFP Plan to use existing platforms Plan to use existing platforms

9. Scope of DC/DP logic 28552.vhd/.vhdtmp files or 98MB (This includes a lot of testbench files!) 28552.vhd/.vhdtmp files or 98MB (This includes a lot of testbench files!) 165880 VHDL lines total of entity/architecture/package/config 165880 VHDL lines total of entity/architecture/package/config 15986 entity-architecture VHDL lines in DP logic (32 files) 15986 entity-architecture VHDL lines in DP logic (32 files) 17478 package VHDL lines in DP logic 17478 package VHDL lines in DP logic

10. Synthesis conversion from ASIC-> FPGA File format and locations (separate entity/architecture, autogenerated packages files for each entity architecture File format and locations (separate entity/architecture, autogenerated packages files for each entity architecture Packages converted from NEC ASIC to Altera logic Packages converted from NEC ASIC to Altera logic

11. Further issues PLLs are needed, need to regenerate PLLs are needed, need to regenerate Dual Port RAM is an ASIC primitive and needs to be converted to Altera RAM block. (Biggest time sink was conversion on unsigned (STD_LOGIC_VECTOR)) Dual Port RAM is an ASIC primitive and needs to be converted to Altera RAM block. (Biggest time sink was conversion on unsigned (STD_LOGIC_VECTOR))

12. VHDL syntax differences Maximum one WAIT statement in a VHDL process. Was used to ensure multi-clock error output generation. May need to correct in the long run. Maximum one WAIT statement in a VHDL process. Was used to ensure multi-clock error output generation. May need to correct in the long run. PLLs currently commented out, and generated off a single off-chip clock. PLLs currently commented out, and generated off a single off-chip clock.

13. Currently…

14. ScreenShot of layout

15. Now proceeding to DataControl chip 140 architecture files compared to 32 of the datapath chip 140 architecture files compared to 32 of the datapath chip Main packaging conversion difficulties should be solved. Main packaging conversion difficulties should be solved. Estimate 5-10X complexity of logic, so potential pitfalls Estimate 5-10X complexity of logic, so potential pitfalls

16. What is needed beyond synthesis Simulation of basic read/write processor access Simulation of basic read/write processor access Understanding of current chipset errata Understanding of current chipset errata Circuit board layout (GTL translation, bus clock rate down from 66MHz) Circuit board layout (GTL translation, bus clock rate down from 66MHz) Boot DOS/Linux/Windows Boot DOS/Linux/Windows Implement compression algorithms Implement compression algorithms

17. Questions?

18. If I have seen further it is by standing on the shoulders of giants. –Isaac Newton, Letter to Robert Hooke, February 5, 1675