1. CBP 2002ITY 270 Computer Architecture1 Digital Logic This Time … Control Path, Arithmetic Ops 12 a U1 34 b Last Time …

2. CBP 2002ITY 270 Computer Architecture2 Data Memory Code Memory ALU X Y W XY W 0 1 7 Digital Logic Where? Control Circuits – CPU control path - system board (later) ALU Structure – add, sub, and, or, not MUXES Address Decoder

3. CBP 2002ITY 270 Computer Architecture3 Boolean Notation, Truth Tables A and B AB A or B A + B NOT A A _ ABC 000 001 010 011 100 101 110 111 Easy Way to write truth tables - count in binary ! A B O A B O A O ABO 000 010 100 111 ABO 000 011 101 111 AO 01 10

4. CBP 2002ITY 270 Computer Architecture4 Digi Logic Design 1 - use Gates A B C O ABCO 000 001 010 011 100 101 110 111 O 0 0 0 1 0 1 1 1 ABC _ _ _ A B C A B C A B C _ _ ABC + ABC + ABC + ABC _ _ _ Majority Function

5. CBP 2002ITY 270 Computer Architecture5 A B C ABC + ABC + ABC + ABC ABC _ _ _ __ _

6. CBP 2002ITY 270 Computer Architecture6 Address Decoder Exercise AB O1O1 O2O2 O3O3 O4O4 001000 010100 100010 110001 A B O1 O2 O3 O4 O1 = AB _ _ A B

7. CBP 2002ITY 270 Computer Architecture7 r0 Decoder Application r1 r2 r0 X Y W XY W Selecting Registers, e.g, add r2,r1,r0 MIPS has 5-bit fields for registers, so are 32 addrdrsrtunused 0 cs r0 Registers decoder

8. CBP 2002ITY 270 Computer Architecture8 MUX Exercise CABO 0000 0010 0101 0111 1000 1011 1100 1111 A B Op C A B O C = 0 A B O C = 1 What is MUX doing here ?

9. CBP 2002ITY 270 Computer Architecture9 MUX is a Selector A B Op C A B C

10. CBP 2002ITY 270 Computer Architecture10 Multibit MUX A B O C A B C

11. CBP 2002ITY 270 Computer Architecture11 MUX Application ALU Y’ Y Selection of Datapath into one ALU input. Datapath Y from instruction add r2,r0,r1 Datapth Y’ from instruction addi r2,r0,4 Sam has been designed so all immediate constants come in via Y’ addrdrsrtunused Immediate bit of op-code

12. CBP 2002ITY 270 Computer Architecture12 Address/Data Bus MUXing CPUMEM addr data CPUMEM add/dat address data address data Multiplexed Address/Data Bus, e.g. PCI Bus Pentium System Bus

13. CBP 2002ITY 270 Computer Architecture13 Digi design 2 - use MUXes ABO 00I1 01I2 10I3 11I4 A B Op In 1 In 2 In 3 In 4 ABO 000 011 101 110 A B Op 0 0 1 1 0 1 01100110 “ Muxes can be used to implement arbitrary combinatorial circuits “

14. CBP 2002ITY 270 Computer Architecture14 MUX Design Exercise 3 input parity detector ABCO 0000 0011 0101 0110 1001 1010 1100 1111

15. CBP 2002ITY 270 Computer Architecture15 Designing Using ROM/RAM A B O 0 0 1 1 0 1 01110111 A B O 0 0 1 1 0 1 01100110 1 1 1 0 0 1 1 0 decoder A B O O Several MUX’es fed with the same AB produce a multibit output. So does a ROM or RAM.

16. CBP 2002ITY 270 Computer Architecture16 Programmable Logic Arrays Fuse ABC _ majority

17. CBP 2002ITY 270 Computer Architecture17 Addition of Binary Numbers 1010 0 1 Sum = 1 Carry = 0 A B 1 1 0 Sum = 0 Carry = 1 A B 1 1 0 1 1 0 0 Multibit add - cascade sum and carry ops.

18. CBP 2002ITY 270 Computer Architecture18 Full Adder ABCiSCo 000 001 010 011 100 101 110 111 S 00 10 10 01 10 01 01 11 Full Adder B A Carry In Carry OutSum

19. CBP 2002ITY 270 Computer Architecture19 Full Adder ABCiOCo 000 001 010 011 100 101 110 111 O 00 10 10 01 10 01 01 11 A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0110100101101001 SUMSUM A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0001011100010111 CARRYCARRY

20. CBP 2002ITY 270 Computer Architecture20 4-bit Adder Full Adder a3a2a1a0 b3b2b1b0 s3 0 Carry Out

21. CBP 2002ITY 270 Computer Architecture21 Let’s Build an ALU + B A Carry In Carry Out S1 S0

22. CBP 2002ITY 270 Computer Architecture22 Issues Concerning Numbers Multiplication and Division Subtraction Negative Numbers Fractional and Real Numbers Characters and Strings

23. CBP 2002ITY 270 Computer Architecture23 Sequential Circuits Traffic Lights Washing Machines Fetch-Execute Cycle

24. CBP 2002ITY 270 Computer Architecture24 Counters T0T1T2T3T4 0 0 0 0 0 10 0 1 00 0 1 10 1 0 0 Clock 4-bit Counter 0 1 0 0 (4) Reset How to get this to sequence 0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 ?

25. CBP 2002ITY 270 Computer Architecture25 Traffic Light Sequencing Clock 4-bit Counter 0 1 0 0 (4) Reset T0T1T2T3 Combinatorial Logic T2 T3 T0 T1

26. CBP 2002ITY 270 Computer Architecture26 Fetch Execute Sequencing T1T2T3T4T5 Fetch Decode, Reg Op ALU Op Mem Access Reg Write ALU 3 1 + -- + ALU Counter Decoder Clock Data Memory Code Memory AL U X Y W XY W 0 1 7

27. CBP 2002ITY 270 Computer Architecture27 Representing Numbers 000 110 001 100 010 011 101 111 5 17 2 6 4 0 3 000 110 001 100 010 011 101 111 -3 1 2 -2 -4 0 3 Let’s take some 3-bit numbers. “2’s Complement” – complement it (0->1 and 1->0) then add 1

28. CBP 2002ITY 270 Computer Architecture28 2’s Complement Properties 000 110 001 100 010 011 101 111 -3 1 2 -2 - 4 0 3 Most Significant Bit (MSB) gives sign. Addition ? 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 -1 0 3 -2 1 3 - 2 = 3 + (-2) = 1 Subtraction by Addition 0 0 1 0 1 0 0 1 1 123123 1 1 1 1 1 0 1 0 1 -1 -2 -3 MSB is Sign Bit !

29. CBP 2002ITY 270 Computer Architecture29 Full Adder a3a2a1a0 b3 b2b1 b0 s3 1 Subtraction by Addition

30. CBP 2002ITY 270 Computer Architecture30 HEX and Chars Hexadecimal Shorthand each nibble rep’d as a character … 1 0 1 1 0 1 1 1 B 7 BinaryHex 0 0 0 0 0 0 11 0 0 1 02 0 0 1 13 0 1 0 04 0 1 5 0 1 1 06 0 1 1 17 1 0 0 08 1 0 0 19 1 0 A 1 0 1 1B 1 1 0 0C 1 1 0 1D 1 1 1 0E 1 1 F Useful in Machine Level Programming and HTML scripting HEXAscii 300 41A 61a 6Dm 0DCR ASCII UNICODE

31. CBP 2002ITY 270 Computer Architecture31 Multiplication 1 3 1 2 2 6 1 3 0 1 5 6 1 1 2 1 1 1 2 2 0 2 3 1 1101 1011 1101 1101 0000 1101 10001111 x x x

32. CBP 2002ITY 270 Computer Architecture32 Multiplication B 1101 C------- - 000001011 Initial values 011011011Add A to B 001101101SHR 100111101Add A to B 010011110SHR No Add 001001111SHR 100011111Add A to B 010001111 A 1 1 0 1 0 0 1 0 1 1C Add/no-add A adder B Add A to B. Then Shift Right (SHR). Look at LSB bit. If this is 1 then Add A to B. A = B = AxB =