1. 1 Modified from  Modified from 1998 Morgan Kaufmann Publishers Chapter Three: Arithmetic for Computers citation and following credit line is included: 'Copyright 1998 Morgan Kaufmann Publishers.' Permission is granted to alter and distribute this material provided that the following credit line is included: 'Adapted from Computer Organization & Design, The hardware/Software Interface, Patterson and Hennesy, second edition, Copyright 1998 Morgan Kaufmann Publishers.' " This material may not be copied or distributed for commercial purposes without express written permission of the copyright holder.

2. 2 Modified from  Modified from 1998 Morgan Kaufmann Publishers Computer Arithmetic Overall Outline The outline for the entire subject of Computer Arithmetic is given below. However, for the sake of readability, the subject is divided into logical sections that can be presented together. The outline for each section will indicate what is covered in that specific section. Introduction Numbers and their representation 2’s Complement Detecting Overflow Basic Review –Binary Conversion –Binary Arithmetic –Hex & Octal Numbers –Basic Boolean Algebra Design Process Design of a “Fast” ALU for MIPS ISA Faster Design, Carry-Look-Ahead Adder

3. 3 Modified from  Modified from 1998 Morgan Kaufmann Publishers Computer Arithmetic Overall Outline continued Additional MIPS Requirements Elements of Design Process Summary of Design Process MIPS Arithmetic Instructions Multiplication methods Division Methods Floating Point Summary

4. 4 Modified from  Modified from 1998 Morgan Kaufmann Publishers Computer Arithmetic Section1 Outline In this unit we will cover: Introduction Numbers and their representation 2’s Complement Detecting Overflow Basic Review –Binary Conversion –Binary Arithmetic –Hex & Octal Numbers –Basic Boolean Algebra

5. 5 Modified from  Modified from 1998 Morgan Kaufmann Publishers Introduction So far we have seen an introduction of how we might map an assembly language, MIPS, to a machine language. We have studied what a machine instruction might look like, how many fields it may have, what and how many instruction formats might be designed, and have seen addressing techniques that might be designed and implemented from the various fields of the instruction formats.

6. 6 Modified from  Modified from 1998 Morgan Kaufmann Publishers Introduction continued What we need to do now, is to learn the basics of how arithmetic operations are done in a simple computer. This will mostly correspond to the “execute” portion of the “fetch & execute” cycle. Once we know how to design arithmetic operations, we can investigate the processor design (Chapter 5) so that the entire fetch & execute cycle can be implemented.

7. 7 Modified from  Modified from 1998 Morgan Kaufmann Publishers Motivation Lets ask some questions, some you already know the answer to, and some that you will learn here: How are negative numbers represented in the computer? What is the largest number that can be represented in a word (integer, real)? What (should) happen if an operation results in a number larger that can be represented in a computer? How do we do arithmetic (add, subtract, multiply, divide, etc) in a computer?

8. 8 Modified from  Modified from 1998 Morgan Kaufmann Publishers In a computer, every thing is represented in terms of bits. Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers Binary numbers (base 2) 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001... Decimal values: 0,..., 2 n -1 Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Numbers

9. 9 Modified from  Modified from 1998 Morgan Kaufmann Publishers Number System 1011 2 = 1×2 0 + 1×2 1 + 0×2 2 + 1×2 3 = 11 10 A number in different systems: Binary:10110110110 Octal: 2 6 6 6 Hexadecimal: 5 B 6

10. 10 Modified from  Modified from 1998 Morgan Kaufmann Publishers Number System You should be able to convert Binary  Hex Binary  Octal You should know about BCD 4 bits/decimal digits, 6 extra codes You should know about ASCII character encoding of binary numbers in 7 bits

11. 11 Modified from  Modified from 1998 Morgan Kaufmann Publishers Negative Numbers Complement in fixed point representation in three forms: Assume 7bits/word Signed Magnitude: 50000101 -51000101 Signed 1’s complement: 50000101 -51111010 Signed2’s complement: +1 50000101 -51111011

12. 12 Modified from  Modified from 1998 Morgan Kaufmann Publishers Sign Magnitude: One's Complement Two's Complement 000 = +0000 = +0000 = +0 001 = +1001 = +1001 = +1 010 = +2010 = +2010 = +2 011 = +3011 = +3011 = +3 100 = -0100 = -3100 = -4 101 = -1101 = -2101 = -3 110 = -2110 = -1110 = -2 111 = -3111 = -0111 = -1 Sign Magnitude: use 1 bit for sign, the rest for magnitude. One's Complement: negative number, x, (a 1 in most significant bit position) are represented as 2 n -x-1 Two's Complement: 2 n -x, so only one zero, (0×2 2 -00=0) Possible Representations

13. 13 Modified from  Modified from 1998 Morgan Kaufmann Publishers Possible Representations Issues: –Which bit should be the sign bit? –Arithmetic is complex, one extra hardware step may be needed for correct sign of the result –Two zero representations! –balance, number of zeros, ease of operations Which one is best? Why? –Come up with a solution that would make the hardware simple. –Leading zeros means positive and leading ones means negative.

14. 14 Modified from  Modified from 1998 Morgan Kaufmann Publishers 32 bit 2’s complement numbers: 0000 0000 0000 0000 0000 0000 0000 0000 two = 0 ten 0000 0000 0000 0000 0000 0000 0000 0001 two = + 1 ten 0000 0000 0000 0000 0000 0000 0000 0010 two = + 2 ten... 0111 1111 1111 1111 1111 1111 1111 1110 two = + 2,147,483,646 ten 0111 1111 1111 1111 1111 1111 1111 1111 two = + 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0000 two = – 2,147,483,648 ten 1000 0000 0000 0000 0000 0000 0000 0001 two = – 2,147,483,647 ten 1000 0000 0000 0000 0000 0000 0000 0010 two = – 2,147,483,646 ten... 1111 1111 1111 1111 1111 1111 1111 1101 two = – 3 ten 1111 1111 1111 1111 1111 1111 1111 1110 two = – 2 ten 1111 1111 1111 1111 1111 1111 1111 1111 two = – 1 ten One larger negative number than positive (minint) maxint minint MIPS

15. 15 Modified from  Modified from 1998 Morgan Kaufmann Publishers Negating a two's complement number: invert all bits and add 1 –remember: “negate” and “invert” are quite different! Converting n bit numbers into numbers with more than n bits: –MIPS 16 bit immediate gets converted to 32 bits for arithmetic –copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 –"sign extension" (lbu vs. lb) Two's Complement Operations

16. 16 Modified from  Modified from 1998 Morgan Kaufmann Publishers Just like in grade school (carry/borrow 1s) 0111 0111 0110 + 0110- 0110- 0101 Two's complement operations easy –subtraction using addition of negative numbers 0111 + 1010 Overflow (result too large for finite computer word): –e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 1000 Addition & Subtraction

17. 17 Modified from  Modified from 1998 Morgan Kaufmann Publishers Addition & Subtraction In 2’s complement, add two numbers including the sign bit, discard any carry out of the sign bit. +50 000101-51 111011 +70 000111+70 000111 +120 001100+210000010 In 1’s complement, add two numbers including the sign bit, if carry out of sign bit increment result by one, and discard carry. +50 000101-51 111010 +70 000111+70 000111 +120 001100+2 1 0 000001 1 0 000010

18. 18 Modified from  Modified from 1998 Morgan Kaufmann Publishers Addition & Subtraction In signed magnitude, we have to compare the signs and do the corresponding operation to determine the sign of the result. The other advantage to 2’s complement arithmetic is that there is only one zero representation: Signed magnitude:0, 000,0001, 000,000 1’s complement:0, 000,0001, 111,111 2’s complement: 0, 000,000 0, 000,000

19. 19 Modified from  Modified from 1998 Morgan Kaufmann Publishers Overflow Lets consider 7 bits + 1 for sign and see when overflow occurs while doing 2’s complement arithmetic: +700 1000110 +800 1010000 +15010010110 Overflow if carry into the sign bit position is different from the carry out of the sign bit position! carry into sign bit 1 0 Carry out of sign bit Sign is negative

20. 20 Modified from  Modified from 1998 Morgan Kaufmann Publishers Overflow In general if two n-digit numbers of the same sign are added to produce an n+1 digit number, overflow occurs. In sign magnitude, the overflow is detected from the carry out bit.

21. 21 Modified from  Modified from 1998 Morgan Kaufmann Publishers No overflow when adding a positive and a negative number No overflow when signs are the same for subtraction Overflow occurs when the value affects the sign: –overflow when adding two positives yields a negative –or, adding two negatives gives a positive –or, subtract a negative from a positive and get a negative –or, subtract a positive from a negative and get a positive Consider the operations A + B, and A – B –Can overflow occur if B is 0 ? –Can overflow occur if A is 0 ? Detecting Overflow

22. 22 Modified from  Modified from 1998 Morgan Kaufmann Publishers Binary Conversion (review) Problem 1:

23. 23 Modified from  Modified from 1998 Morgan Kaufmann Publishers Binary Conversion (review) Problem 2:

24. 24 Modified from  Modified from 1998 Morgan Kaufmann Publishers Binary Conversion Problem 2 (cont.):

25. 25 Modified from  Modified from 1998 Morgan Kaufmann Publishers Binary Arithmetic (review)

26. 26 Modified from  Modified from 1998 Morgan Kaufmann Publishers Binary Arithmetic (review) Overflow Detection with Two’s Complement: If the CarryIn of the MSB equals the CarryOut of the MSB, no overflow occurs. Otherwise overflow occurs.

27. 27 Modified from  Modified from 1998 Morgan Kaufmann Publishers Hexadecimal (Base 16) Numbers (review)

28. 28 Modified from  Modified from 1998 Morgan Kaufmann Publishers Octal (Base 8) Numbers (review)

29. 29 Modified from  Modified from 1998 Morgan Kaufmann Publishers Logic Review Now a quick review of logic gates and Boolean algebra. You may refer to Appendix B of your textbook for detailed study.

30. 30 Modified from  Modified from 1998 Morgan Kaufmann Publishers Common Logical Gates (review) Truth table

31. 31 Modified from  Modified from 1998 Morgan Kaufmann Publishers Demorgan’s Law (review)

32. 32 Modified from  Modified from 1998 Morgan Kaufmann Publishers Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true Show the truth table for these three functions. Review: Boolean Algebra & Gates (review)

33. 33 Modified from  Modified from 1998 Morgan Kaufmann Publishers Show the Boolean equations for these three functions. Show an implementation for each OP equation consisting of inverters, AND, and OR gates. Note: –All equations can be put in Sum of Products (SOP) form. –In this class, answers should always be given in the simplest SOP form (unless otherwise stated). Boolean Algebra & Gates (review) (cont.)

34. 34 Modified from  Modified from 1998 Morgan Kaufmann Publishers To obtain simplest Sum of Products (SOP) boolean equation, use a Karnaugh map or boolean algebra. Boolean Algebra & Gates (review) (cont.) C B A

35. 35 Modified from  Modified from 1998 Morgan Kaufmann Publishers Boolean Algebra & Gates (review) (cont.)

36. 36 Modified from  Modified from 1998 Morgan Kaufmann Publishers Design A One-bit Full Adder Lets build the truth table for inputs A, B, and carry-in C in, generating the outputs S and carry-out, C out : A B C in C Cout S 0 0 00 0 0 10 1 0 1 00 1 0 1 11 0 1 0 00 1 1 0 11 0 1 1 01 0 1 1 11 C in AB 00 01 11 10 0 1 0101 1010 S C in AB 00 01 11 10 0 1 0010 0111 C out

37. 37 Modified from  Modified from 1998 Morgan Kaufmann Publishers Design A One-bit Full Adder Therefore for S we have: S = A’BC’ + AB’C’ + A’B’C + ABC =(A’B + AB’)C’ + (A’B’ + AB)C =(A  B)C’ + (A  B)’C =A  B  C And for C out we have: C out =AB + BC + AC OR C ou =AB + A’BC + AB’C =AB + C(A’B + AB’) =AB + C( A  B) This is a combinational circuit in which the output is a function of present inputs C in AB 00 01 11 10 0 1 0010 0111