1. Thanushan Kugathasan, CERN Plans on ALPIDE development 02/12/2014, CERN

2. In-pixel circuit Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 2 Strobe Front-end analog output (pix_out) The front-end acts as an analogue delay line 2 µs peaking time When Strobe is asserted, the front-end binary output is latched into the pixel state register Pixel state register readout by a zero suppression circuit (AERD)

3. Front-end / comparator Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 Analog BiasPurpose VRESET_PPMOS active reset diode bias IRESETPMOS active reset max current VRESET_DDiode active reset diode bias IBIASFront-End bias current (40 nA) ITHRFront-End threshold current (0.5 nA) IDBInverter stage threshold VCASPFront-End PMOS cascode VCASNFront-End NMOS cascode, tuning of the DC output VPULSE_LOWPulsing Voltage Level (Low) VPULSE_HIGHPulsing Voltage Level (High) Analog references generated by an on-chip 8-bit DAC 3 P w ~ 40 nW/pixel => 5 mW/cm 2

4. pALPIDEfs_V2 - Sectors Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 4 Sector nwell diameter Spacing pwell opening Reset Input PMOS W/L 02 µm 6 µmPMOS0.22 1*2 µm 6 µmPMOS0.92 22 µm4 µm10 µmPMOS0.22 32 µm4 µm10 µmDiode0.22 PMOS reset Diode reset Pulsing capacitor: 0.16 fF Input routing line Input PMOS pwell opening = nwell diameter + 2. spacing * Some pixels in sector 1 have antenna protection diode for the transistor connected to the bias lines.

5. In-pixel logic Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 2 Configuration bits: Pixel pulsing Pixel masking Signals buffered from the periphery Pixel State register Test charge injection Input from priority encoder Output to priority encoder 5

6. Matrix Read-Out scheme 6 Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 … STATE VALID ADDRESS AERD PIXEL Front-end Periphery Digital Readout PIXEL Front-end RESET STATE RESET STATE RESET STATE RESET SYNC 10 512 STATE PIXEL Front-end RESET STATE RESET 512 0 1 511 512 rows DACs VALID ADDRESS SYNC 10 VALID ADDRESS SYNC 10 AERD 512 double columns Address Encoder Reset Decoder (AERD) Zero-suppression with priority encoder logic

7. Priority Encoder Logic Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 7 Unit block of the hierarchical tree element (repeated block) STATE[0] STATE[1] STATE[2] STATE[3] PRIORITY LOGIC Fast OR VALID ADDRESS[1] ADDRESS[0] SYNC[0] SYNC[1] SYNC[2] SYNC[3] SYNC HIERARCHY N HIERARCHY N-1 HIERARCHY N+1 Priority Hierarchical arbiter tree structure -> reduces loads, 5 levels to encode 1024 pixels Fully combinatorial asynchronous circuit without clock propagating into the matrix -> reduction of power & noise ▪ Provide active pixel address to periphery ▪ Propagate SYNC(RESET) from periphery to active pixel ▪ Process repeated until all hits are read out -in pixel memories reset one by one at each clock cycle -readout duration depends on occupancy

8. Pixel layout Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 4 metal layers routing Two power domains: Analog (Front-end) Digital (Pixel logic and AERD) 8

9. Priority Encoder (AERD) Pixel matrix detail Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 9 Pixel Column (Left) Pixel Column (Right) 56 µm

10. Summary and outlook Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 pALPIDEfs_V2 implements the same in-pixel circuit as in pALPIDEfs_V1 1024 x 512 pixels (28 µm x 28 µm) New sectors Minor layout changes pALPIDEfs_V1 pixel sensor is fully efficient in-pixel front-end with power consumption of 40 nW per pixel. reverse substrate bias offers more operation margin Goals for the next design: Multiple in-pixel state registers. Reduction of the threshold spread (~ 18 e - in pALPIDEfs_V1) Reduction of the circuit input capacitance contribution. Reduction of the front-end bias parameters. Studies on pixel front-end outpt signal shaping time (pile-up, trigger latency). 10

11. 11Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2

12. Multiple in-pixel State Register Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 3 Pixel state registers 12 Strobe Memory to be written (front-end state latch) Mem_sel Memory to be read and reset by the AERD readout

13. Pixel Logic I/O Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 13 SignalDescription Logic level 01 INPUT PULSE_TYPE Pulse type selection Enable DPULSEEnable APULSE PULSE CMOS pulse see DPULSE and APULSE PIXCNFG_DATA Configuration data D-LATCH data line PIXCNFG_COLSEL Column selection DisableEnable PIXCNFG_ROWSEL Row selection DisableEnable PIXCNFG_REGSEL Register selection Pulse reg.Mask reg. PIX_OUT_B Pixel front-end output Active low STROBE_B Strobe window (1 per state register bit) Active low MEM_SEL_B State register bit to be interfaced to the priority encoder Active low PRST_B State register reset (global) Active low PIX_RESET State register reset from priority encoder Effective on falling edge OUT STATE State register value to priority encoder (if MASK_EN = 0) Active high

14. State Register 14 Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 3 x NAND SR Latches

15. State bit cell 15 Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 Set logic Reset logic Set logic and reset have the same transistor level implementation (x2)

16. State register output selection 16 Thanushan Kugathasan - Pixel matrix in pALPIDEfs_V2 Transistor level