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Published byLouise Stafford Modified over 2 years ago

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NxN pixel demonstrator

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Time to Digital Converter (2) Tapped delay line –128 cells, 100ps Two hit registers –One per both leading and trailing edge 7 bit encoding

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Delay Locked Loop - DLL Delay locked loop –Voltage controllable delay line (VCDL) of 128 delay cells –Phase detector –Charge pump –Output buffers τ0τ0 τ1τ1 τ N-2 τ N-1 PDCP VCDL UP DOWN Ref CLK DLL CLK V CTRL t0t0 t1t1 t N-2 t N-1

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Time to Digital Converter Christian’s TDC downscaled to 100ps –Only delay cell and its bias circuit need to be redesigned Device sizes scaled down by factor of 10 –pmos loads 1.2 µm, nmos current source 1.2 µm, input pair nmos 2 µm I bias = 47 µA, V supply = 1.2 V –56 µW per delay cell 7.2 mW for 128 delay cells (corresponding to a 12.8 ns clock period = 78.125MHz) –Scaled down from 1.64 mA (2 mW) With slide difference in Current Density (times 4) due to the impractical device dimensions Delay τ D = 98 ps –Easily adjusted to 100 ps with control voltage

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Delay Cell Output

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Delay Buffer Output – full cycle

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Summary of Delay Cell Device sizes scaled down by factor of 10 –pmos loads 1.2 µm, nmos current source 1.2 µm, input pair nmos 2 µm I bias = 47 µA, V supply = 1.2 V –~56 µW per delay cell 7.2 mW for 128 delay cells (corresponding to a 12.8 ns clock period = 78.125MHz) –Scaled down from 1.64 mA (2 mW) With slide difference in Current Density (times 4) due to the impractical device dimensions Delay τ D = 98 ps –Easily adjusted to 100 ps with control voltage Buffer –36.22 µA –Appears to be enough to drive all the 90 hit registers (single-ended)

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Hit Registers – Single-Ended Christian’s design made for 32 cells –Each hit register consists of 32 DFFs 32 x 7 x 7 (µm) 2 = 225 x 7 (µm) 2 In our design 2 x 45 Hit registers (each 128 DFFs) covering all 45 columns –128x7x7 (µm) 2 = 900 x 7 (µm) 2 –90x900x7 (µm) 2 = 900 x 630 (µm) 2 Total average power consumption for 90 single-ended hit registers = 67 mW

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Hit Registers – Differential Differential hit register –Two possible designs: Differential with CMOS logic output (full swing 0 – 1.2V) Differential with CML input and output (low voltage swing 0.8V – 1.2V) –Total average power consumption of ~950 mW (increase by a factor 14!) –CML: Decreases the noise by a factor of 2/3 (2 peak noise, 3 rms noise) –CMOS: Decreases the noise by factor 1.1/1.6 i N_peak (µA)i N_rms (µA)P av (µW) SE33.6843.3555.84 DIFF30.7892.10580.62 DIFF_CML16.4471.24083.71

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Differential or Single-ended? Ground line noise through 1nH inductance Red: single-ended DFF Orange: differential DFF w/ CMOS logic output –Small signal levels only at input stage Blue: differential DFF w/ CML output –Small signal levels at input and output stages

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Differential or Single-ended? Differential: –Lower rms noise – high power consumption –Access to digital libraries Differential CML: –Low peak and rms noise – high power consumption –No access to digital libraries Every digital circuit needs to be re-designed differential Single-ended: –Access to digital libraries –Low power - high noise BUT: –All digital logic is out side the pixels All pixels are purely analog –No analog circuits outside the pixels Easy to isolate digital and analog parts -Separate power supply and ground lines -Guarding between pixel array and periphery

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Summary of TDC Differential Voltage Controllable Delay Line (VCDL) –128 differential delay cells Hit registers –2 regs per column (45 columns) => 90 Hit regs –Average power consumption of 67 mW Simulated with each register changing its state once per clock cycle for ten cycles –Usually not all register change state and not all register banks are active every clock cycle => average power consumption may be much less Total average power consumption –128 delay cells w/ buffers: 128 x 85 µA x 1.2 V = 13 mW –2 x 45 Hit register: 67 mW ( differential: 964 mW ) –Total of ~80mW ( differential: 977 mW )

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The End

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Differential or Single-ended? Genuinely differential means: –Symmetric (exactly 180 degree phase difference) signals biased with common current source Importance of mismatch –Not complementary out-of-phase full-swing CMOS signals Two benefits in CML signals –Symmetric differential signals cancel the even order components of noise and interference –Current starving and small signal levels Decreasing the voltage swing, switching current and therefore switching noise (PSRR)

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HCC Derived Clocks. Generated Clocks The HCC generates two clocks from the ePLL 160 MHz clocks and the chip 40 MHz clock, used as a reference: An 80 MHz.

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