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PSROC, February 2, 2005 Sun Yat-San University Ching-Cheng Hsu National Taiwan University On behalf of NuTel Group Outline :  Overview of NuTel Experiment.

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Presentation on theme: "PSROC, February 2, 2005 Sun Yat-San University Ching-Cheng Hsu National Taiwan University On behalf of NuTel Group Outline :  Overview of NuTel Experiment."— Presentation transcript:

1 PSROC, February 2, 2005 Sun Yat-San University Ching-Cheng Hsu National Taiwan University On behalf of NuTel Group Outline :  Overview of NuTel Experiment & Electronics Schematics  Preliminary measurements of Electronics  Conclusion and Prospect

2 PSROC, February 2, 2005 Sun Yat-San University Using Earth / mountain as target Signals : Cherenkov light from   showers     Only sensitive to  : e : electron shower mostly absorbed in mountain  no extensive air shower generation  appearance

3 PSROC, February 2, 2005 Sun Yat-San University Mirror R : 2.1 m Mirror Diameter: 1.2 m Corrector Lens : aspheric formula Lens Diameter : 0.9 m 0.07 m 2 m Designed with OSLO optical design software. The spot size smaller than our pixel size :0.5 degree! correct spherical aberration

4 DAQ PMT Preamp. UV filter Trigger Total 1024 channels Start readout 10 bit x 40 MHz Pipelined ADC 16 RAM x 256 x 16 per 8 channels Mirror Trigger FPGA FADC buffer RAM ADC control FPGA (x4) cycle RAM Charge-Sharing Board PSROC, February 2, 2005 Sun Yat-San University 16 CSB 16x 64 ch. 16 MAPMT 16x64 Pixels 32 DCM, 32x32 ch. Using two telescopes for stereo observation Preamp 64 x 16

5 Feasibility Study of Calibration the NuTel Prototype Detector with Crab Nebula PSROC, February 2, 2005 Sun Yat-San University 15 Slave DCM Master DCM Daisy-Chain of Trigger Request Trigger Decision, System Clock & Reset Single Board Computer DAQ operation rate can be up to 500 Hz with negligible dead time. One chassis processes information from 512 channels

6 Feasibility Study of Calibration the NuTel Prototype Detector with Crab Nebula PSROC, February 2, 2005 Sun Yat-San University Sum up all the charges ADC saturated 0.002mV The total charges we calculate from ADC counts is proportional to the DAC input voltage.

7 Feasibility Study of Calibration the NuTel Prototype Detector with Crab Nebula PSROC, February 2, 2005 Sun Yat-San University Al Box Size 185 cm (length) x 23cm x26cm (height) MAPMT Preamp High voltage cable 150 cm The walls inside the box are covered by black blanket. Connected to DCM

8 LED pulse 1KHz, pulse width 75 ns LED with voltage from 1.92 V to 2.2 V. PMT operational voltage from 650 V to 750 V. Totally 33 combinations. PMT Pixel ID PSROC, February 2, 2005 Sun Yat-San University rms : smaller than 0.5 ADC count Average all operation conditions Pedestals for each pixel are steady Here are few channels with negative or around 0 pedestals. Maximal r.m.s noise is 0.77 ADC count. Typical noise is between 0.6 and 0.7 ADC counts.

9 1 2 8 9 1 57 Hammamatsu H7546 With PMT Voltage 700 V, LED : 2.2 V PMT + Preamp +DCM : Maybe due to non-uniform light or/and effective area of the channels. PSROC, February 2, 2005 Sun Yat-San University

10 The total components of noise σ: σ 2 = {σ no_sig 2 } + G*M + {σ with_sig 2 } * M 2 # of photons coming to PMT, has a Poisson distribution, so mean value (M) and RMS (σ 0 ) charge distribution of the PMT are G = M/N = σ 0 2 / M Y= σ 2 X=M Y= σ 2 X=M G = 2.84 G = 6.41 G = 13.96 Y= σ 2 X=M G = 2.97 G = 6.75 G = 13.88

11 The pixels on the two sides have large light collection. HV 800 V PSROC, February 2, 2005 Sun Yat-San University Relative charge between pixels

12 PSROC, February 2, 2005 Sun Yat-San University Conclusion:  We have developed an electronic system for NuTel experiment.  We developed some methods for calibrating and measuring our hardware system.  We are studying the performance of each component. Prospect :  We are planning to go to the high mountains for real testing at the end of this year.

13 PSROC, February 2, 2005 Sun Yat-San University to another DCMfrom preamplifier to DMM calibration cPCI connector Control FPGA Control FPGA Trigger FPGA Trigger FPGA ADC FPGA ADC FPGA ADC FPGA ADC FPGA ch. 0 ch. 1 ch. 2 ch. 3 ch. 4 ch. 5 ch. 6 ch. 7 ch. 24 ch. 25 ch. 26 ch. 27 ch. 28 ch. 31 ch. 30 ch. 29 PLX PCI 9054 PLX PCI 9054 MUXMUX MUXMUX MUXMUX MUXMUX 40 MHz oscillator 40 MHz oscillator DAC switch CPLD Flash RAM Flash RAM TTL  LVDS TTL  LVDS 5V  3.0V 3.3V  1.8V +5V  –5V DC–DC +5V  –5V DC–DC JTAG Power control FET MUXMUX MUXMUX

14 PSROC, February 2, 2005 Sun Yat-San University Inject pulse from DAC into ADC On average one ADC channel 2mV

15 PSROC, February 2, 2005 Sun Yat-San University Light source are homogenous within 1 to 2 degree.

16 16 Calculation N of photoelectrons during every system clock Cherenkov photons pulse Preamplifier output ADC code Simple difference Δ A ~Q Delay due pipeline ADC System clock (40 MHz) Delay due calculations Reconstructed photons pulse ANAN A N+1 15/16A N ΔA Simple difference (A N+1 - A N ) will be noisy in hard BG conditions, (ΔA = A N+1 – 15/16 A N) is much more stable ~exp(-t/387ns) exp(-25/387) = 15/16

17 Data flux in NuTel system interrupt Trigger decision II MAPMT Preamp. II MAPMT Preamp. 16  32=512 pixels (8  16  ) FOV 16  32=512 pixels (8  16  ) FOV Daisy-chain of Trigger request System card, LINUX 15 Slave DCM Master-B DCM Master-A DCM interconnections for TIMING COINCIDENCE, System CLOCK, System RESET

18 # of photons coming to PMT, has a Poisson distribution, so mean value (M) and RMS (σ 0 ) of the pedestal-subtracted charge distribution of the PMT are G = M/N = σ 0 2 / M But the total components of σ: σ 2 = {σ 1 2 + σ 2 2 } + G*M + {σ 3 2 + σ 4 2 } * M 2 noise of electronics without signal (σ 1 ) noise of PMT gain: signal from photoelectron has the Poisson distribution with  3 (σ 2 ) noise of electronics proportional to the signal (σ 3 *M) noise due jitter between signal and system clock (σ 4 *M) If constant and quadratic components of the noise is smaller than the linear components, G = σ 2 /M

19 Using 2 identical telescopes for the background rejection Random Background with NSB flux Geometrical Trigger: 1 km away from a 1 PeV e - shower Central pixel passed high-level threshold (HL) & at least N neighboring pixels passed low-level threshold (LL) Hardware Trigger: There are geometrical Triggers in any place (direction) at the same time  one system clock (25 ns) in both telescopes On-line Software Trigger: There are geometrical Triggers in the same place (direction) at the same time in both telescopes Off-line Hardware Trigger: More detail data processing, calculation/ searching a possible source on the sky

20 Data processing in hardware/firmware MAPMT Signal sharing preamplifier ADC Calculation N photoelectrons Programmable thresholds 32-channels Trigger logic Cycle RAM like digital delay line 32-channels Trigger logic Trigger daisy chain Trigger Decision logic from the second detector Buffer RAM like event storage counter Trigger Interrupt to the System card if 16 events are ready cPCI bus Geometrical Trigger Timing coincidence

21 Feasibility Study of Calibration the NuTel Prototype Detector with Crab Nebula PSROC, February 2, 2005 Sun Yat-San University

22 Feasibility Study of Calibration the NuTel Prototype Detector with Crab Nebula PSROC, February 2, 2005 Sun Yat-San University

23 Y= σ 2 X=M Y= σ 2 X=M G = 2.84 G = 6.41 G = 13.96 Y= σ 2 X=M G = 2.97 G = 6.75 G = 13.88


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