1. Chap 2. Combinational Logic Circuits

2. 2.1 Binary Logic and Gates Logic Gates
electronic circuits that operate on one or more input signals to produce an output signal

3. 2.1 Binary Logic and Gates

4. 2.2 Boolean Algebra deal with binary variables and logic operations
F = X + Y' Z
deal with binary variables and logic operations
with three basic logic operations AND, OR, NOT
Implemented with logic circuits

5. 2.2 Boolean Algebra Basic Identities of Boolean Algebra
most basic identities of Boolean algebra

6. 2.2 Boolean Algebra Algebraic Manipulation
Boolean algebra is a useful tool for simplifying digital circuits
F = X'YZ + X'YZ' + XZ
= X'Y (Z+Z') + XZ
= X'Y 1 + XZ
= X'Y + XZ

7. 2.2 Boolean Algebra popular tools 1. X + XY = X (1 + Y) = X
2. XY + XY' = X (Y + Y') = X
3. X + X'Y = (X + X') (X + Y) = X + Y
4. X (X + Y) = X + X Y = X (1 + Y) = X
5. (X + Y)(X + Y') = X + YY' = X
6. X (X' + Y) = XX' + XY = XY
7. (consensus theorem)
XY + X'Z + YZ = XY + X'Z
dual (X+Y)(X'+Z)(Y+Z) = (X+Y)(X'+Z)

8. 2.2 Boolean Algebra Complement of a Function F = X'YZ' + X'Y'Z

9. 2.3 Standard Forms Sum of product Products of sum Minterms & Maxterms
Product terms (minterms)의 sum
Products of sum
Sum terms (maxterms)의 products
Minterms & Maxterms
Product (Sum) terms in which all the variables appear exactly once, either un-complemented or complemented
Ex) 4 minterms for 2 variables X & Y
X'Y', X'Y, XY', & XY

10. 2.3 Standard Forms
mj’=Mj

11. 2. 3 Standard Forms - sum of products E(X,Y,Z) =  m(0,1,2,4,5)
- product of sums
E(X,Y,Z)' =  m(3,6,7)

12. 2.4 Map Simplification – 3 variables

13. 2.4 Map Simplification – 3 variables
F1(X,Y,Z) =  m(3,4,6,7) F2(X,Y,Z) =  m(0,2,4,5,6)
(Ex) F2(X,Y,Z) =  m(1,3,4,5,6)

14. 2.4 Map Simplification – 4 variables

15. 2.4 Map Simplification – 4 variables
F(W,X,Y,Z)
=  m(0,1,2,4,5,6,8,9,12,13,14)
= Y' + W'Z' + XZ'
F = A'B'C' + B'CD' + A'BCD' + AB'C'
= B'D' + B'C' + A'CD'

16. 2.4 Map Simplification – 4 variables
From sum-of-products to product-of-sums
complement the function
F(A,B,C,D) =  m(0,1,2,5,8,9,10)
F' = AB + CD + BD‘
F = (A'+B')(C'+D')(B'+D)

17. 2.4 Map Simplification – don’t care
Ex) F(A,B,C,D) =  m(1,3,7,11,15)
d(A,B,C,D) =  m(0,2,5)
F = CD + A'B' = CD + A'D

18. 2.6 NAND and NOR Gates NAND gate a universal gate
because any digital system can be implemented with it

19. 2.6 NAND and NOR Gates Two-Level Implementation
easy to implement with NAND gates, if the function is in sum of products form
(Ex) F = AB + CD
F = ( (AB)‘)’+ ((CD)‘)’ = ( (AB)' (CD)' )' = AB + CD

20. 2.6 NAND and NOR Gates
F(X,Y,Z) =  m(1,2,3,4,5,7)

21. 2.6 NAND and NOR Gates NOR gate dual of the NAND operation
another universal gate
implementation of NOT (inverter), AND, OR

22. Chap 3. Combinational Logic Design

23. 3.1 Combinational Circuits
logic circuits for digital systems: combinational vs sequential
Combinational Circuit (Chap 3)
outputs are determined by the present applied inputs
performs an operation, which can be specified logically by a set of Boolean expressions
Sequential Circuit (Chap 4)
logic gates + storage elements (called flip-flops)
outputs are a function of the inputs & bit values in the storage elements (state of storage elements is a function of previous inputs)
output depends on the present values of inputs & past inputs

24. 3.4 Design Procedure Procedure to design combinational circuits
1) Determine required number of inputs & outputs & assign a letter symbol to each
2) Derive the truth table
3) Obtain simplified Boolean functions for each output
4) Draw the logic diagram
5) Verify the correctness of the design
Truth Table
n input variables: 2n binary numbers
output functions give the exact definition of comb circuit simplified by method, such as algebraic manipulation, map method, computer programs

25. 3.4 Design Procedure

26. 3.4 Design Procedure – code converter
BCD to Excess-3 Code Converter

27. 3.4 Design Procedure – code converter

28. 3.4 Design Procedure – code converter
Two-level AND-OR logic diagram
W = A + BC + BD
= A + B(C + D)
X = B'C + B'D + BC'D'
= B'(C + D) + BC'D‘
Y = CD + C'D‘
= (C D)‘
Z = D'

29. 3.4 Design Procedure Ex) BCD to Seven-Segment Decoder
outputs (a, b, c, d, e, f, g)
7 four-variable maps

30. 3.5 Decoders n비트 이진정보 => 2n (이하)의 출력 Decoders
N-to-m-line decoders (m < 2n)
generate 2n (or fewer) minterms of n input variables
Ex) 3-to-8-line decoder (3 inputs & 8 outputs)

31. 3.5 Decoders
Ex) binary-to-octal conversion

32. 3.5 Decoders - Expansion
3-to-8-line decoder with two 2-to-4-line decoders
if A2=0, upper is enabled;
if A2=1, lower is enabled.

33. 3.5 Decoders Combinational Circuit Implementation Ex) a binary adder
S(X,Y,Z) = S m(1,2,4,7)
C(X,Y,Z) = S m(3,5,6,7)

34. 3.6 Encoders perform the inverse operation of a decoder
2n (or less) input lines and n output lines
Ex) Octal-to-binary encoder
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

35. 3.7 Multiplexers n개의 선택입력에 따라 2n개의 출력 중에 하나를 선택하여 출력
입력단자: 2n input lines and n selection variables
Ex) 22-to-1-line multiplexer
Also, called data selector or MUX

36. 3.7 Multiplexers
Quadruple 2-to-1-Line Multiplexer

37. 3.7 Multiplexers Combinational Circuit Implementation
Any Boolean function of n variables can be implemented with a multiplexer with (n-1) selection inputs and (2n-1) data inputs
Ex) F(A,B,C,D) =  m(1,3,4,11,12,13,14,15)
Implemented with 23-to-1 MUX

38. 3.7 Multiplexers
Ex) F(A,B,C,D) =  m(1,3,4,11,12,13,14,15)

39. 3.7 Multiplexers Demultiplexer (DEMUX) selectors
perform the inverse operation of a multiplexer
receives information from a single line and transmits it to one of 2n possible output lines
Ex) 1-to-4-line demultiplexer
the input E has a path to all 4 outputs,
selected by two selection lines S1 and S0
“identical to a 2-to-4 line decoder with enable input”
selectors