1. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).

2. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Hardware description languages n Textual languages for describing hardware: –structure; –function. n Most people today use textual languages rather than schematics for most digital design. –Schematics make poor use of screen space.

3. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Major HDLs n Two major HDLs designed for simulation: –VHDL; –Verilog. –Similar capabilities but somewhat different language philosophies. n EDIF is a standard netlist format.

4. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Simulation vs. programming n Simulation tags computations with times. –Must know when signals change to properly simulate hardware. n Simulation is parallel. –Many statements can execute at the same (simulation) time. –Just like hardware.

5. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Types of simulation n Compiled code simulation. –Generate program that evaluates a hardware block. –Operational details within the hardware block are lost. n Event-driven simulation. –Propagate events through simulation. –Don’t simulate a block until its inputs change.

6. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Event-driven simulation n An event is a change in a net’s value. n An event has two components: –value; –time. timet=35 ns net1=0 @ 35 ns net event net1

7. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR n Propagate events only when nets change value. n If an input change doesn’t cause an output change, no event is propagated. 0 1 1 0 no event 1 0

8. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Timewheel n The timewheel is a data structure in the simulator that efficiently determines the order of events processed. n Events are placed on the timewheel in time order. n Events are taken out of the head of the timewheel to process them in order.

9. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Timewheel operation a b c 1 0 1 a=1 @ 0 ns netlist timewheel b=1 @ 1 ns 1 c=0 @ 2 ns 0 time

10. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Order of evaluation n Order of evaluation is important. –Causality must be obeyed. n Evaluating events in the wrong order can cause inaccurate results.

11. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Order of evaluation example a b c 0 0 0 netlist timewheel b=1 @ 1 ns 1 d=1 @ 2 ns 1 d e 1 e=0 @ 4 ns 0 1 time

12. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Modeling n Structural modeling describes the connections between components. –Netlists are structural models. n Behavioral models describes the functional relationship between inputs and outputs. –Similar to programming but values are events.

13. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR HDLs language constructs n Must be able to define component types. –A model may be behavioral or structural. n May be able to define abstract data types. –A wire may carry an enumerated value. –Multi-valued simulation may be defined using abstract data types. n May be able to define modules to control the scope of names.

14. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Testbenches n A testbench is a model used to exercise a simulation. –Provides stimulus. –Checks outputs. n Testbenches help automate design verification. –Rerun edited module against testbench. –Run models at behavioral, RTL levels against the same testbench.

15. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Synthesis subsets n VHDL and Verilog were designed for simulation. n A synthesis subset is: –synthesizable; –produces consistent simulation results. n Different tools may use different synthesis subsets.

16. Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Register-transfer synthesis n Most common type of synthesis. n Synthesizes gates from abstract RT model. –Registers are explicit. –Some tools will infer storage elements---be careful. n Optimized for performance, area, power.