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Audio DAC Matt Smith Alfred Wanga CSE598A/EE597G Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006.

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Presentation on theme: "Audio DAC Matt Smith Alfred Wanga CSE598A/EE597G Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006."— Presentation transcript:

1 Audio DAC Matt Smith Alfred Wanga CSE598A/EE597G Analog-Digital Mixed-Signal CMOS Chip Design Spring 2006

2 Digital audio has become widespread in home/consumer electronics Portable Music Players (CD, SACD, MP3) PC Audio (Sony/Philips Digital Interface Format) Home Theater Systems (DVD, Optical Interconnects) Digital Audio

3 Design Philosophy - Goals High Quality Audio Applications  Accurate Reproduction  Low Noise Versatile  Support for Standard Sampling Rates  Specifications that allow use in Various Audio Applications

4 Figures of Merit Sampling Rate  Support common sampling speeds (96kHz) Bit Depth  Finer Resolution → Better fidelity (>= 16bit) Total Harmonic Distortion + Noise (THD+N)  Important for audio applications (< 1% THD+N) Signal to Noise Ratio (SNR)  Equal or better than digital source (>= 100dB)

5 Voltage-output thermometer DAC Current-output thermometer DAC Binary-weighted DAC R-2R DAC Requires 2 n identical resistors Requires 2 n -1 identical resistors Requires 2 n unique current sources Challenge: Requires precise resistors to get LSB resolution DAC Architecture

6 Current-output Voltage-output Output buffer required to provide low output resistance Output voltage swing limited by op-amp Output voltage limited to 1/3 V ref R-2R DAC

7 Project Schedule Week #1 (2/5 – 2/11)  Finalize design goals and specifications Week #2 (2/12 – 2/18)  Finalize and test inverter and buffer Week #3 (2/19 – 2/25)  Finalize and test digital components (latches, gates)

8 Project Schedule Week #4 (2/26 – 3/4)  Begin operational amplifier design Week #5 (3/5 – 3/11)  Finalize design for operational amplifier Week #6 (3/12 – 3/18)  Finalize resistor design  Project Progress Report

9 Project Schedule Week #7 (3/19 – 3/25)  Finalize and test voltage reference circuitry Week #8 (3/26 – 4/1)  Complete final circuit design and layout Week #9 (4/2 – 4/8)  Complete circuit layout and testing Week #10 (4/9 – 4/13)  Final Project Presentation


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