1. MCS51 - lecture 5

2. Lecture 5 2/28 Interrupts in MCS51 Step work Power consumption reducing

3. MCS51 - external interrupts 3/28 2 inputs: INT0 i INT1; level or falling edge active; enabled/disabled by bits EX0 i EX1 in IE register; control register: TF1 8F TR1 8E TF0 8D TR0 8C IE1 8B IT1 8A IE0 89 IT0 88 TCON88h IE1 - INT1flag IT1 - if set INT1 active on falling edge IE0 - INT0 flag IT0 - if set INT0 active on falling edge

4. MCS51 - external interrupts 4/28 ITx IEx INTx 0101 EXx INTx inputs are tested each machine cycle logical structure of ext. interrupt circuit

5. MCS51 - external interrupts 5/28 Interrupts active low-level If ITx = 0 the state of IEx flag changes automatic due to state of INTx input. Software altering of IEx flag is then impossible. To initiate level-active external interrupt (to set IEx flag), the appropriate bit of port P3 should be cleared. Signal return from low to high level at input INTx before starting interrupt service routine causes missing the interrupt. Leaving low level signal at input INTx by service routine causes immediate start of this procedure machine cycle N-1machine cycle Nmachine cycle N+k high level detection 3 / 4 c.m. low level detection IEx 3 / 4 c.m. INTx

6. MCS51 - external interrupts 6/28 Interrupts active falling edge If ITx = 1 flag IEx is set after detection of falling edge on input INTx: time condition for correct detection of falling edge interrupt: t INTH, t INTL > T CM machine cycle N-1machine cycle Nmachine cycle N+1 falling edge detection 3 / 4 c.m. INTx IEx 3 / 4 c.m. t INTH t INTL T CM IEx flag automatically cleared during start of interrupt service routine the first instruction cycle of INTx service routine

7. MCS51 - interrupt system 7/28 Features: vectorial - each interrupt source has own, fixed address of service routine begin: start addresses satisfy an equation: ISR_address = k·8+3, k=0,1,... priority - fixed priorities of interrupt vectors (lower if vector address higher), additionally priority groups are accessible (2 - standard, 4 - some MCS51 extensions); multilevel (2 - standard, 4 - some MCS51 extensions); disabled after reset;

8. MCS51 - interrupt system 8/28 Control registers: Interrupt enabling register: EA - if set enables interrupt system ET2 - if set enables timer/counter 2 interrupt (EXF2 or TF2) ES - if set enables SIO interrupt (RI or TI) ET1 - if set enables timer/counter 1 interrupt (TF1) EX1 - if set enables external interrupt INT1 (IE1) ET0 - if set enables timer/counter 0 interrupt (TF0) EX0 - if set enables external interrupt INT0 (IE0) EA AF - AE ET2 AD ES AC ET1 AB EX1 AA ET0 A9 EX0 A8 IEA8h

9. MCS51 - interrupt system 9/28 - BF - BE PT2 BD PS BC PT1 BB PX1 BA PT0 B9 PX0 B8 IPB8h Priority register: Setting chosen bit of IP assign interrupt to higher level priority group PT2 - timer/counter 2 interrupt PS - SIO interrupt PT1 - timer/counter 1 interrupt PX1 - external INT1 interrupt PT0 - timer/counter 0 interrupt PX0 - external INT0 interrupt

10. MCS51 - interrupt system 10/28 Interrupt system structure

11. MCS51 - interrupt system 11/28 Interrupt system vectors (ISR_address): INT0 03h timer 0 0Bh INT1 13h timer 1 1Bh SIO (RI+TI) 23h timer2 (TF2+EXF2) 2Bh

12. Recognising interrupts and starting service routine: 1. Each machine cycle (at phase S5P2, i.e. at 5 / 6 m.c.) interrupt flags are checked. 2. In next machine cycle: if EA=1 & individual enabling flags of requested interrupts are set & following condition are fulfilled: interrupt service routine of the same or higher priority then new interrupt isn’t executed; current machine cycle is the last cycle of current instruction; current instruction isn’t RETI, neither any instruction changing: interrupt priority or enabling control registers; then after finishing current instruction cycle MCS51simulates execution of LCALL ISR_address (ISR_address starting address of service routine). MCS51 - interrupt system 12/28

13. MCS51 - interrupt system 13/28 The starting of interrupt service routine automatically clears flags: TF0, TF1 IE0, IE1 only if interrupt are falling-edge active If external interrupt is low-level active, the service routine should cause the return of signal to high level - it will clear IEx flag. SIO port flags (TI, RI) and timer/counter 2 flags (TF2, EXF2) should be cleared by software, inside the service routine, after recognising the true interrupt source.

14. MCS51 - interrupt system 14/28 Latency time of interrupt service: lower limit: m.c. int. flag testing m.c. interrupt arbitration 2x m.c. LCALL service routine 1st m.c. service routine T INTLAT > 3T MC upper limit (assumption: no other service routine is executed) end of normal instruction m.c. interrupt arbitration 2x m.c. LCALL service routine 1st m.c. service routine T INTLAT < 9T MC specific instruction for example RETI 4x m.c. instruction MUL or DIV m.c. int. flag testing interrupt flag int. flag

15. MCS51 - interrupt system 15/28 Interrupt service routine - recommended structure : storing on stack registers used by routine, especially: PUSH PSW, other registers (A, B, DPH, DPL, etc.) switching to another register bank clearing interrupt reason: clearing interrupt request & if needed - software clearing interrupt flag (like RI,TI) restoring registers from stack RETI

16. MCS51 - interrupt system 16/28 Single-level interrupt system, all priority bits have the same value M timer #0 service TF0 SIO service RI INT0 service INT1 service M automatic changes software changes IE1 INT1 IE0 INT0 M - main program

17. MCS51 - interrupt system 17/28 Two-level interrupt system, bits PX1,PS=1 (higher level) other bits=0 M timer service #0 TF0 SIO service RI INT0 service INT1 service IE1 INT1 IE0 INT0 M automatic changes software changes M - main program

18. MCS51 - interrupt system 18/28 Multi-level interrupt system, priority can have the same state System accessible by special structure of interrupt service routines: storing on stack registers used by routine, especially: PUSH PSW, other registers (A, B, DPH, DPL, etc.) switching to another register bank clearing interrupt reason: clearing interrupt request & if needed - software clearing interrupt flag (like RI,TI) ACALL fini_int_srv restoring registers from stack RET fini_int_srv : RETI

19. MCS51 - interrupt system 19/28 Multi-level interrupt system - cont. M timer service #0 TF0 SIO service RI INT1 service IE1 INT1 IE0 INT0 M automatic changes software changes execution of fini_int_srv INT0 service timer #0 service M - main program

20. MCS51 - interrupt system 20/28 Multi-level interrupt system - cont. ATTENTION: internal RAM can be overfilled by stack in multi-level interrupt system Different priorities of interrupt vectors decide only about the sequence of servicing requested interrupts after enabling interrupt system by execution of RETI instruction. System works like multi-level interrupt system without priority.

21. MCS51 - interrupt system extensions 21/28 1. Increasing the number of interrupt sources more external interrupts; additional built-in peripherals. 2. Increasing the number of priority levels from 2 to 4 (dual IP registers)

22. MCS51 - step work 22/28 Low level-active external interrupt can be used to step work Ass. INT0 input connected with switch breaking the connection with ground INT0 (P3.2) INT0 ISR is used to servicing step work debugging step work software service (SWSS) JNB P3.2,$ JB P3.2,$ RETI waiting for low level at INT0 waiting for high level at INT0 Low level active of INT0 causes the calling of its ISR debugged prog. E SWSS 111111100R SWSS 111100R SWSS11111111110000R /INT0 E - enabling interrupts 1 - waiting for „1” 0 - waiting for „0” R - RETI

23. MCS51 - power saving 23/28 SMOD---GF1GF0PDIDL PCON87h Power saving modes are met in CMOS chips Standard control register: IDL - if set enables idle mode PD - if set enables power down it has higher priority then bit IDL GF1, GF0 - flags for user usage, absent in some MCS-51 ATTENTION: the bits of PCON aren’t direct addressable

24. MCS51 - power saving 24/28 Idle mode instruction setting bit IDL is last executed; oscillator still works; interrupt system works; built-in peripherals work; port pins left unchanged ( see datasheets ); content of internal data RAM and SFR are stored; supply current reduced several times;

25. MCS51 - power saving 25/28 Idle mode - cont. return to normal work by: - enabled interrupt request: appropriate service routine will be executed, and next processor will return to the instruction following the one, which set bit IDL; if idle mode is still needed, program should look like that: enable_idle:ORLPCON,#1 SJMPenable_idle optional flags GF0 i GF1 can be used too - hardware reset but it resets microcontroller and initiates SFR

26. MCS51 - power saving 26/28 Power down mode instruction setting bit PD is last executed; oscillator is stopped; interrupt system doesn’t work; built-in peripherals don’t work; port pins left unchanged ( see datasheets ); content of internal data RAM and SFR are stored; supply voltage can be reduced to 2V (1V for CL chips); supply current can be reduced more than 100 times (! structure of circuits connected to ports is important); return to normal work only by hardware reset - but it resets SFR

27. MCS51 - power saving 27/28 Other power saving solutions: Slow down mode (for example in 515A, 517, 517A) enabled by switch on additional prescaler in oscillator by setting additional control bit; instructions are executed slower; built-in peripherals work slower; supply voltage can be reduced to 2V (1V for CL chips); supply current reduced the same times as oscillator frequency; return to normal work by clearing control bit.

28. MCS51 - power saving 28/28 Other power saving solutions - cont.: Return from power-down mode by: enabled external interrupt (level-active); interrupt from special second counter; Additional control bits for idle and power-down modes: IDLE & IDLS and PDE & PDS. Then, to enable chosen mode we have to use the sequence of 2 instructions, example: MOVA,PCON ORLA,#1;IDLE:=1 ANLA,#0DFh;IDLS:=0 MOVPCON,A;write to PCON XRLA,#21h;IDLE:=0,IDLS:=1 MOVPCON,A; write to PCON