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Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics Puneet Gupta, University of California, Los Angeles Andrew B. Kahng, University of California,

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Presentation on theme: "Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics Puneet Gupta, University of California, Los Angeles Andrew B. Kahng, University of California,"— Presentation transcript:

1 Eyecharts: Constructive Benchmarking of Gate Sizing Heuristics Puneet Gupta, University of California, Los Angeles Andrew B. Kahng, University of California, San Diego Amarnath Kasibhatla, University of California, Los Angeles Puneet Sharma, Freescale Semiconductor, TX Research funded in part by NSF

2 Outline Motivation Solving Eyechart Topologies Experiments for Suboptimality Study Results 2

3 Why is Sizing Important? Sizing  Effective way of optimizing for power, speed and area  Tunable parameters  Gate-width  Threshold voltage  Gate-length  Supply voltage etc. Sizing problem seen at all stages of RTL to GDS flow Power recovery crucial during post-layout phase 3

4 Why Study Suboptimality? Literally hundreds of gate sizing methods exist Common heuristics/algorithms:  Linear Programming, Lagrangian Relaxation, Convex Optimization, Dynamic Programming, Geometric Programming, Sensitivity based gradient-descent, Simulated Annealing etc. Which heuristic is better? No systematic way to compare, so far How suboptimal are these heuristics? Does a heuristic’s performance depend on  Circuit topology?  Characteristics of the cell library? No prior work focuses on these aspects 4

5 Sizing Problem Formulation Sizing problem could be discrete or continuous Discrete sizing problem is NP-hard Common designs are standard cell-based and discrete We focus only on discrete sizing problem Problem: Leakage power minimization under timing constraints Circuits are purely combinational Gate sizing alone is tested and not logic optimization capability 5

6 Our Contributions We generate artificial combinational circuits called eyecharts Gate’s delay depends only on  Gate size  Total load capacitance Eyecharts can be solved optimally using Dynamic Programming (DP) A variety of eyecharts are generated by varying  Circuit topology  Power-Size, delay-size characteristics of library Suboptimalities of existing heuristics studied under these variations Leakage optimization details are presented Extensions to dynamic power optimization are easy 6

7 Outline Motivation Solving Eyechart Topologies Experiments for Suboptimality Study Results 7

8 What are Eyecharts? Chain MESH STAR Chain, Mesh and Star proposed Each can be solved optimally for the assumed delay model Stage of a gate is its logic level from the PI Levelized nature of eyecharts enables optimal sizing by DP 8

9 What are Eyecharts? Chain MESH STAR Stage1 Stage2 Stage3 Stage4 Stage5 PI PO Chain, Mesh and Star proposed Each can be solved optimally for the assumed delay model Stage of a gate is its logic level from the PI Levelized nature of eyecharts enables optimal sizing by DP 9

10 Solving a Chain Optimally InputLeakage Delay cappower Load Load = 3 = 6 Size 1 3 5 3 4 Size 2 6 10 1 2 10

11 Solving a Chain Optimally Stage 3 Stage 1 Stage 2 6 INV1 INV2 INV3 D max = 8 InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 11

12 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 3 Stage 1 Stage 2 ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 12

13 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 13

14 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? Load = 3 InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 14

15 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 6 15

16 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 16

17 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 17

18 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size ? InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 18

19 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 ? ? 2 ? ? 3 5 1 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? 2 ? ? 3 ? ? 4 ? ? 5 ? ? 6 ? ? 7 ? ? 8 ? ? Stage 3 Stage 1 Stage 2 Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 19

20 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 1 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 Stage 3 Stage 1 Stage 2 Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 20

21 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 Stage 2 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 21

22 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 22

23 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size INV2 Excess Total delay budget power size 1 3 3 10 InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 23

24 Solving a Chain Optimally 6 INV1 INV2 INV3 D max = 8 INV2 Excess Total delay budget power size 1 3 3 10 size 2 1 5 15 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 24

25 Solving a Chain Optimally 6 8 20 1 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 Load = 6 25

26 Solving a Chain Optimally 6 8 20 1 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size Budget Power Size INV3 Excess Total delay budgetpower size 1 4 4 20 size 2 2 6 25 InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 Load = 6 26

27 Solving a Chain Optimally 6 8 20 1 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size Budget Power Size INV3 Excess Total delay budgetpower size 1 4 4 20 size 2 2 6 25 InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 Load = 6 27

28 Solving a Chain Optimally 6 8 20 1 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 INV3 Excess Total delay budgetpower size 1 4 4 20 size 2 2 6 25 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 Load = 6 28

29 Solving a Chain Optimally 6 8 20 1 INV1 INV2 INV3 D max = 8 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 Load = 6 29

30 Solving a Chain Optimally 6 1 10 2 2 10 2 3 5 1 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 2 10 2 3 10 2 4 5 1 5 5 1 6 5 1 7 5 1 8 5 1 3 20 2 4 15 1 5 15 2 6 10 1 7 10 1 8 10 1 4 20 2 5 15 1 6 15 2 7 10 1 8 10 1 8 20 1 INV1 INV2 INV3 Load = 6 Budget Power Size 6fF OPTIMIZED CHAIN D max = 8 Stage 1 Stage 2 Stage 3 Stage 1 Stage 2 Budget Power Size Budget Power Size InputLeakage Delay cappower Load Load 3 6 Size 1 3 5 3 4 Size 2 6 10 1 2 Load = 3 Load = 6 Load = 3 Load = 6 30

31 Solving Mesh Optimally Stage with multiple gates represented with composite cell Mesh to chain conversion C2 C3 C4 A1 A2 B1 B2 Stage1 Stage2 Stage3 Stage4 Stage5 A1B2 A1 A2 A1 31

32 Solving Mesh Optimally Stage with multiple gates represented with composite cell Delay, power numbers for all size combinations for all output load combinations Delay, power table of B1 Mesh to chain conversion C2 C3 C4 A1 A2 B1 B2 Stage1 Stage2 Stage3 Stage4 Stage5 A1B2 InputPower Delay cap Load Load =12 = 24 Size 1 6 10 6 8 Size 212 20 2 4 Size Power Delay (B1,B2) (1,1)30 12 (1,2)506 (2,1)40 12 (2,2)604 Size Power Delay (B1,B2) (1,1)30 16 (1,2)50 8 (2,1)40 16 (2,2)60 8 LOAD = 12 LOAD = 24 STAGE 4 A1 A2 A1 32

33 Solving Star Optimally Star solved by converting it to chain Composite cells formed for stages with multiple gates A1 A2 B C1 C3 B Stage 1 Stage2Stage 3 C1 & C3, Composite cells for Stages 1 & 3 33

34 Hybrid Eyecharts Chain 1 and Chain 2 Chain 3 and Chain 4 Sample hybrid eyechart A A A A A B B B BA AA A C A A A A A B B B B A A A A A B B B B A A A A A B B B BA C Chain, mesh, star daisy-chained for arbitrarily large hybrid eyecharts Mesh/chain arbitrarily inserted along each PI/PO chain Hybrid eyechart solved optimally by ultimately reducing it to a chain A A A Chain 1 Chain 2 Chain 3 Chain 4 PO1 PO2 PI2 PI1 34

35 Arbitrary Extensions to Eyecharts Arbitrary extensions potentially add more realism to eyecharts Such topologies solved using partial enumeration No levelization restriction One example is multi-output mesh PO PI MESH 35

36 Arbitrary Extensions to Eyecharts Arbitrary extensions potentially add more realism to eyecharts Such topologies solved using partial enumeration No levelization restriction One example is multi-output mesh PO 1 PO 2 PO 3 PI MULTI-OUTPUT MESH PO PI MESH 36

37 Arbitrary Extensions to Eyecharts Arbitrary extensions potentially add more realism to eyecharts Such topologies solved using partial enumeration No levelization restriction One example is multi-output mesh PO 1 PO 2 PO 3 PI MULTI-OUTPUT MESH PO PI MESH 37

38 Outline Motivation Solving Eyechart Topologies Experiments for Suboptimality Study Results 38

39 Experimental Setup Heuristics compared  Comm1, Comm2: Two different commercial gate-sizing/leakage- optimization tools  GS: Sensitivity-based sizing tool with sensitivity metric =  LP: Linear programming tool [Nguyen et.al, ISLPED ’03]  SBS: Sensitivity-based sizing tool with sensitivity metric = [Gupta et.al, IEEE Tran. on CAD ’06] Explored power, delay tradeoffs with size  LP-LD: Linear increase in power, linear increase in delay  LP-NLD: Linear increase in power, nonlinear increase in delay  EP-LD: Exponential increase in power, linear increase in delay  EP-NLD: Exponential increase in power, nonlinear increase in delay Experiments to explore dependence of suboptimality on  Circuit size, circuit topology  Delay-Size, power-size tradeoff  Granularity of the cell library 39

40 Library Characteristics LP-LD 8.43% Gate Sizing 8 LP-NLD 0.3% Gate Sizing 8 EP-LD 8.43% V t, gate-length 3,3 EP-NLD 0.3% V t, gate-length 3,3 Library Model RMS fittingOptimizationDefault # error (delay) context sizes/variants The sizing choices for EP-LD and EP-NLD models are V t variants and gate-length variants Capacitance does not vary across V t variants Capacitance increase with gate-length for gate-length variants Delay values are fitted to a 65 nm industrial library Suboptimalities are calculated as 40

41 Outline Motivation Solving Eyechart Topologies Experiments for Suboptimality Study Results 41

42 Circuit Topology Impact Mesh-only Chain-only Suboptimality % Star-only Mesh is the toughest topology 42

43 Circuit Size Impact #Gates Comm1 RT Comm2 RT LP RT GS RT % % % % 1796 21.31 14 15.81 16 15.7 56 23.1 24 10026 21.29 261 16.73 365 15.5 450 23.5 309 25993 20.98 540 15.75 539 15.4 1617 23.2 512 51015 21.3 721 16.21 722 15.1 2458 23.5 921 Suboptimality relatively constant with circuit size 10K-gate benchmarks for the rest of the experiments LP runtime does not scale well 43

44 Circuit Size Impact #Gates Comm1 RT Comm2 RT LP RT GS RT % % % % 1796 21.31 14 15.81 16 15.7 56 23.1 24 10026 21.29 261 16.73 365 15.5 450 23.5 309 25993 20.98 540 15.75 539 15.4 1617 23.2 512 51015 21.3 721 16.21 722 15.1 2458 23.5 921 Suboptimality relatively constant with circuit size 10K-gate benchmarks for the rest of the experiments LP runtime does not scale well 44

45 Impact of Timing Constraints LP-LD delay model: Linear increase in delay with size Suboptmalities are close to zero for very tight or very relaxed constraints 45

46 Impact of Nonlinearity in Delay LP-NLD delay model: Nonlinear increase in delay with size Gap between sensitivity-based methods and LP tool becomes narrow 46

47 Impact of Power Tradeoff EP-NLD delay model: Exponential increase in power LP suffers significantly due to snapping error 47

48 Gate-length Biasing Scenario Tools in general slightly worse compared to V t assignment Capacitance varies across gate-length variants 48

49 Effect of Granularity Higher granularity has much larger benefits for exponential compared to linear power tradeoff LP-NLD EP-NLD 49

50 Extensions to Slew Dependent Delay Delay of a gate depends on input slew Output slew of a gate depends on  Gate size  Output load capacitance Slew propagation is not considered Optimal solution not guaranteed due to the need to maintain slew consistency Experiments show suboptimality is still significant (5% to 35%)

51 Conclusion Eyecharts can help diagnose and benchmark gate sizing heuristics  Suboptimality depends on circuit topology and power-/delay-size tradeoffs Existing heuristics be highly suboptimal  2% to 46% (gate sizing)  6% to 54% (V t -assignment)  14% to 49% (gate-length biasing) Ongoing work includes benchmarks  Based on fanout distribution  For joint sizing, multi-Vt, gate-length variant optimization Benchmarks and code can be downloaded at http://nanocad.ee.ucla.edu/Main/DownloadForm 50

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