1. Hardware Design and The Petri Net Abhijit K. Deb SAM, LECS, IMIT, KTH Kista, Stockholm

2. Abhijit K. Deb2 Outline  Petri net and HW design  Characteristics  Simulation  Example: A set of communicating FSM  Verification  Conclusion

3. Abhijit K. Deb3 Petri Net and HW Modeling  Petri net is a general formalism to represent discrete event systems  For HW design, Petri net has been used in many different ways:  synthesis  HW/SW partitioning  simulation & verification

4. Abhijit K. Deb4 Petri Net Characteristics  Parallelism or concurrency is modeled better in a Petri net  The composition of state machines is complex; composition of Petri nets is simple  Petri nets are asynchronous in nature, however when synchronization is needed, that is also easy to model  There is no inherent measure of time in a Petri net

5. Abhijit K. Deb5 Synthesis using Petri Net Verilog STG Mapped Netlist VL2aSTG petrify C2 C3 C1 C2 C3 C1 clock

6. Abhijit K. Deb6 Simulation  Often, systems are modeled as a set of communicating FSMs  Problem:  FSMs are good for modeling sequential behavior but modeling concurrency and memory is difficult  state explosion  data value

7. Abhijit K. Deb7 Forming the Petri Net  Each state of the communicating FSMs are represented by a place, called state-place.  All synchronization signals are represented by two places:  a high place  a low place  A token can not exist in both of the places and both places can not be empty as well  Arcs are drawn between input places to transitions and transitions to output places  Reset signal gives the initial distribution of tokens in different places

8. Abhijit K. Deb8 FSM - PN FSM Representation – / cs=0, rws=0 sel=1, wr=1 / cs=1, rws=1 t1 cs t2 S2 S1 cs rws wr sel S1S2 Petri Net Representation

9. Abhijit K. Deb9 Timing  Introduce clock-place to represent time  The clock-place is an input place for all transitions synchronous with that clock  Appearance of token in a clock-place represent the arrival of a clock edge and advances simulation time  For a system with multiple clocks, multiple clock-places are needed, where tokens appear according to the ratio of the speeds of the clocks involved

10. Abhijit K. Deb10 Handling Data  Storage (e.g., memory, register) and interconnect (e.g., bus) hold data  Data signals are viewed as placeholders  The placeholders can be of different type, an integer, array or a composite type like a record  They are updated with a transition firing either by an assignment operation or by a C-function call

11. Abhijit K. Deb11 Simulation Procedure 1.incidence matrix is formed for the Petri net derived from the FSM description of the system 2.reset signal gives the initial states of the signals and the communicating FSMs 3.clock place gets tokens to advance simulation time 4.using the present state of the net, enabled transitions are marked, that gives the firing vector 5.enabled transition(s) can be fired at any order 6.next state of the system is computed using the following: x’ = x + uA 7.based on the new state, if a given condition is true then update the placeholders for data values using an assignment operation or a C function call 8.repeat from step 3 as long as there are enabled transitions 1.incidence matrix is formed for the Petri net derived from the FSM description of the system 2.reset signal gives the initial states of the signals and the communicating FSMs 3.clock place gets tokens to advance simulation time 4.using the present state of the net, enabled transitions are marked, that gives the firing vector 5.enabled transition(s) can be fired at any order 6.next state of the system is computed using the following: x’ = x + uA 7.based on the new state, if a given condition is true then update the placeholders for data values using an assignment operation or a C function call 8.repeat from step 3 as long as there are enabled transitions

12. Abhijit K. Deb12 A Network of FSM G1 G3 G2 G4 G n-1 1 ………… reqFrm2=1 / Grant2 =1 reqFrm1 =0 reqFrm1=1 / Grant1 =1 reqFrm1 =0 / Grant1 =0 reqFrm2 =0 GnGn reqFrm2=0 / Grant2 =0 Arbiter IO_wr =1 / reqFrm2 =1 IO_rd =1 / reqFrm2=1 Grant2 =1 / rdReq =1 Ack =1 / rdReq =0 Ack = 0 / dtRdy = 0 reqFrm2 =0 Ack =1 / wrReq =0 dtRdy = 1 Grant2 =1/ wrReq =1 dtRdy = 1 / Ack = 1 C1C2 C7 C3C6C4 C5C8 Core dtRdy =0 / Ack = 0 reqFrm2 =0 M1 M4 M2 M3 dtRdy = 1 / Ack =0 rdReq = 0 / Ack = 0 dtRdy =1 rdReq =1 / Ack =1 wrReq = 1 / Ack = 1 Memory Ack =1 / dtRdy = 0

13. Abhijit K. Deb13 The Arbiter ClCl ChCh BlBl BhBh AlAl AhAh

14. Abhijit K. Deb14 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

15. Abhijit K. Deb15 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

16. Abhijit K. Deb16 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

17. Abhijit K. Deb17 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

18. Abhijit K. Deb18 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

19. Abhijit K. Deb19 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

20. Abhijit K. Deb20 Petri net Representation wrRq M1 M2 C2 C3 A2 A1 busRq grant wrRq IO_wr C1 Memory Core arbiter t6 t5 t4 t3 t2 t1

21. Abhijit K. Deb21 Specification Verification  Conservation: One token must exist in one of the high or low place of a signal, both of them can not be empty simultaneously.  Boundedness: Tokens can not grow in one of the places.  Safety property: the system will not get into a specific undesirable configuration, e.g., a deadlock or the emission of undesired output.  Liveness property: Some desired configuration will be visited eventually or infinitely often (fairness).

22. Abhijit K. Deb22 Conclusion  Systems can be simulated using Petri nets  The Petri net representation is bounded  The number of places is the summation of all the states plus twice the number of all the synchronization signals  Provides the necessary glue between different parts of the system, which is needed to perform a system simulation  The simulation shows dynamic behavior of the system  It is possible to perform certain specification verification using Petri net

23. Abhijit K. Deb23 Thank You!  Questions?