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1 Advanced Digital Design Synthesis of Control Circuits by A. Steininger and J. Lechner Vienna University of Technology

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 2Outline Control Circuits Control Circuits Petri Nets & Signal Transition Graphs Petri Nets & Signal Transition Graphs Properties Properties Common PN/STG fragments Common PN/STG fragments Synthesis of SI control circuits Synthesis of SI control circuits State Encoding State Encoding Next-state functions Next-state functions Implementation Implementation Synthesis tool: Petrify Synthesis tool: Petrify

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 3 Control Circuits Control logic essential part of asynchronous circuits Control logic essential part of asynchronous circuits How to specify? How to specify? How to implement? How to implement? Control ? Latch Comb.Logic Latch Comb.Logic Latch ReqReqReqAckAckAck Req Ack Req Ack

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 4 Petri Nets (PNs) For modelling concurrent systems For modelling concurrent systems Directed graph with nodes and arcs Directed graph with nodes and arcs Nodes: places, transitions Nodes: places, transitions Places can be marked with tokens Places can be marked with tokens Transition is enabled (allowed to fire) if all input places have tokens Transition is enabled (allowed to fire) if all input places have tokens When a transitions fires: When a transitions fires: Token removed from all input places Token removed from all input places Token added to each output place Token added to each output place

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 5STGs Restricted subclass of petri nets Restricted subclass of petri nets PN transitions = signal transitions PN transitions = signal transitions Simple places omitted (places with a single input and a single output) Simple places omitted (places with a single input and a single output) Places/arcs represent causal relationships between signal transitions Places/arcs represent causal relationships between signal transitions Marking represents circuit state Marking represents circuit state

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 6 PN/STG - Example Muller C-gate Source: [Sparso 06]

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 7 Properties of STGs I Input free choice Input free choice Alternative transitions only controlled by mutually exclusive inputs Alternative transitions only controlled by mutually exclusive inputs 1-bounded 1-bounded Max. one token per place Max. one token per place Liveness Liveness STG is live iff from every reachable marking, every transition can eventually fire STG is live iff from every reachable marking, every transition can eventually fire

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 8 Typical PN/STG Fragments Choice Merge ForkJoin

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 9 PN/STG Fragments - Example Source: [Sparso 06]

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 10 Properties for STGs II STGs can be implemented as speed- independent circuits. Requirements: STGs can be implemented as speed- independent circuits. Requirements: Consistent state assignment Consistent state assignment In any execution, any transition alternates between rising and falling In any execution, any transition alternates between rising and falling Persistency Persistency Enabled signals will eventually fire, cannot be disabled by other transition Enabled signals will eventually fire, cannot be disabled by other transition Complete state coding (CSC) Complete state coding (CSC) Different markings must represent different states Different markings must represent different states

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 11 Speed-Independence (SI) Delay-model: speed-independence Delay-model: speed-independence Arbitrary gate delays (bounded but unknown) Arbitrary gate delays (bounded but unknown) Ideal zero-delay wires Ideal zero-delay wires Source: [Sparso 06]

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 12 STG Synthesis Specification State graph State Graph with CSC Next-State functions Decomposed functions Gate netlist Reachability analysis State encoding Boolean minimization Logic decomposition Technology mapping

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 13Specification Source: [Sparso 06]

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 14 State Graph b+ c+ b- c- a+ b+ d+ c+ d- a- (a,b,c,d)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 15 Excitation Regions for Output Signal c b+ c+ b- c- a+ b+ d+ c+ d- a- QR1(c+) ER1(c+) ER2(c+) ER1(c-)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 16 Quiescent Regions for Output Signal c b+ c+ b- C- a+ b+ d+ c+ d- a- QR1(c+) QR1(c-)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 17 Next-State Functions KV Diagram for c cd ab xxF 01Rxx1 110R11 100xxx b+ c+ b- C- a+ b+ d+ c+ d- a- QR1(c+) ER1(c+) ER2(c+) ER1(c-) QR1(c-)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 18 Atomic Complex Gate Implementation cd ab xxF 01Rxx1 110R11 100xxx c = d + a‘b + bc Attention: Decomposition into simple gates can introduce hazards!

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 19 State-holding Gates Implementation Signals toggle between excitation and quiescent/stable regions Signals toggle between excitation and quiescent/stable regions ER(c+) QR(c+) ER(c-) QR(c-) etc. ER(c+) QR(c+) ER(c-) QR(c-) etc. Implementation with SR-latches, C- gates or generalized C-gates possible Implementation with SR-latches, C- gates or generalized C-gates possible Generalized C- element Source: [Sparso 06]

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 20 State-holding Gates Set/Reset Functions c = Set + c ∙ Reset‘ c = Set + c ∙ Reset‘ Set ∙ Reset = 0 Set ∙ Reset = 0 Set Function: Set Function: must contain all states in ER(c+) must contain all states in ER(c+) may contain states in QR(c+) may contain states in QR(c+) may contain not reachable states may contain not reachable states Reset Function: Reset Function: must contain all states in ER(c-) must contain all states in ER(c-) may contain states in QR(c-) may contain states in QR(c-) may contain not reachable states may contain not reachable states

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 21 State-holding Gates Implementation cd ab xxF 01Rxx1 110R11 100xxx Set function: c-set = d + a‘b

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 22 State-holding Gates Implementation cd ab xxF 01Rxx1 110R11 100xxx Set function: c-set = d + a‘b Reset function: c-reset = b‘

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 23 State-holding Gates Implementation cd ab xxF 01Rxx1 110R11 100xxx Set function: c-set = d + a‘b Reset function: c-reset = b‘

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 24 State-holding Gates Hazards cd ab xxF 01Rxx1 110R11 100xxx b+ c+ b- c- a+ b+ d+ c+ d- a- 010010010010 010010010010 0101 0 010010010010

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 25 State-holding Gates Monotonic Cover Constraint A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint) A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint) cd ab xxF 01Rxx1 110R11 100xxx Hazardous set function: c-set = d + a‘b

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 26 State-holding Gates Monotonic Cover Constraint A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint) A cube (product term) may only be entered through ER states (monotonic cover or unique entry constraint) cd ab xxF 01Rxx1 110R11 100xxx Fixed set function: c-set = d + a‘bc‘

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 27 Example VME Bus Controller LDS+LDTACK+D+ DTACK- DTACK+DSr-D- DSr+ LDS-LDTACK- VME Bus Controller DSr DTACK LDS LDTACK D STG of Read Cycle

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 28 VME Bus Controller CSC Conflict DSr DSr+ DSr+ DTACK- DTACK- DTACK- LDTACK-LDTACK- LDTACK- LDS-LDS-LDS- LDS+ LDTACK+ D+ DTACK+ DSr- D- (DSr, DTACK, LDTACK, LDS, D)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 29 VME Bus Controller CSC Conflict LDS+LDTACK+D+ DTACK- DTACK+DSr-D- DSr+ LDS-LDTACK LDS+LDTACK+D+ DTACK- DTACK+DSr-D- DSr+ LDS-LDTACK

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 30 Resolving CSC Conflict Concurrency Reduction Solution I: Remove conflict state by concurrency reduction Solution I: Remove conflict state by concurrency reduction DSr DSr+ DSr+ DTACK- DTACK- DTACK- LDTACK-LDTACK- LDTACK- LDS-LDS-LDS- LDS+ LDTACK+ D+ DTACK+ DSr- D-

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 31 Resolving CSC Conflict Concurrency Reduction Solution I: Remove conflict state by concurrency reduction Solution I: Remove conflict state by concurrency reduction DSr DSr+ DTACK- DTACK- DTACK- LDTACK-LDTACK- LDTACK- LDS-LDS- LDS+ LDTACK+ D+ DTACK+ DSr- D-

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 32 Resolving CSC Conflict Concurrency Reduction Concurrency reduction reflected by adding an arc to the STG specification. Concurrency reduction reflected by adding an arc to the STG specification. Introduces timing assumption (LDS- before DSr+) Introduces timing assumption (LDS- before DSr+) LDS+LDTACK+D+ DTACK- DTACK+DSr-D- DSr+ LDS-LDTACK-

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 33 Resolving CSC Conflict Adding State Signal Solution II: Inserting an internal state signal to make conflict states unique Solution II: Inserting an internal state signal to make conflict states unique DSr DSr+ DSr+ DTACK- DTACK- DTACK- LDTACK-LDTACK- LDTACK- LDS-LDS-LDS- LDS+ LDTACK+ D+ DTACK+ DSr- D- (DSr, DTACK, LDTACK, LDS, D, CSC) CSC CSC-

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 34Petrify Synthesis of speed independent control circuits from STG specifcations Synthesis of speed independent control circuits from STG specifcations Simple text format for describing STGs Simple text format for describing STGs Petrify can solve CSC problem Petrify can solve CSC problem Public domain tool Public domain tool Developed at different universities Developed at different universities

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 35 Petrify - Example.model cgate.inputs a b.outputs c.graph a+ c+ b+ c+ c+ a- c+ b- a- c- b- c- c- a+ c- b+.marking { }.end

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 36Petrify Set of command-line tools Set of command-line tools petrify: synthesis command petrify: synthesis command write_sg: derives state graph write_sg: derives state graph draw_astg: draws STGs/state graphs draw_astg: draws STGs/state graphs Different circuit implementations Different circuit implementations Complex gates (-cg) Complex gates (-cg) Generalized C-elements (-gc) Generalized C-elements (-gc) Specific target library (-tm) Specific target library (-tm)

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Lecture "Advanced Digital Design"© A. Steininger & J. Lechner / TU Vienna 37Summary Control logic essential part of asynchronous circuits Control logic essential part of asynchronous circuits PNs/STGs convenient for modeling control circuits PNs/STGs convenient for modeling control circuits STGs need to fulfill certain properties STGs need to fulfill certain properties Input-free choice, 1-bounded, CSC, etc. Input-free choice, 1-bounded, CSC, etc. Synthesis from STGs to SI gate implementations possible Synthesis from STGs to SI gate implementations possible Tool available: Petrify Tool available: Petrify

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