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Testing of ROM. Functional faults: 1.Main SAF; 2.Amplifier SAF; 3.R/W line SAF; 4.Selection CS SAF; 5.Data line SAF; 6.Data line interruption; 7.Data line.

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Presentation on theme: "Testing of ROM. Functional faults: 1.Main SAF; 2.Amplifier SAF; 3.R/W line SAF; 4.Selection CS SAF; 5.Data line SAF; 6.Data line interruption; 7.Data line."— Presentation transcript:

1 Testing of ROM. Functional faults: 1.Main SAF; 2.Amplifier SAF; 3.R/W line SAF; 4.Selection CS SAF; 5.Data line SAF; 6.Data line interruption; 7.Data line short-circuit; 8.Data line cross-talk; 9.Address line SAF; 10.Address line interruption; 11.Address line short-circuit; 12.Interruption in decoder; 13.Selection of the wrong address; 14.Turning to several addresses; 15.Faults in transition (0 to 1and vice versa); 16.Dependence of data between slots. Classification of faults: 1.SAF stuck at 0/1 faults 1-6; 2.CF coupling faults faults 7,8 and 16; 3.TF transition faults fault 15; 4. AF address decoder faults faults 9-14. Faults in ROMs and their classification

2 Constant faults: 1.Connection faults; 2.Broken components; 3.Faults in manufacturing; 4.Faults in design. Unstable faults: 1.Environment (temp. humidity, pressure...); 2.Vibration; 3.Feed; 4.Electromagnetic field, static electricity, ground; 5.Bad connections; 6.Timing; 7.Changes in resistance and capacity, 8.Noise; 9.Ageing. Possible causes of faults in ROMs.

3 DC A0A0 A 3 11 0 1 2 3 b1b1 b2b2 Programmable ROM DC A0A0 A 3 0 1 2 3 +v b1b1 b2b2 1 1 1 1 0 0 0 1 1 1 01 Fuse Mask-programmed ROM

4 DC A0A0 A 3 0 1 2 3 +v b1b1 b2b2 1 1 1 1 0 0 0 1 1 1 tension 2U 1 tension U 1 tension 0 The only fuse that falls under the voltage of 2U resulting in its melting. Programming of EPROM

5 p nn Silicon floating gate Silicon fixed gate V ss V dd V gg EPROM array V dd WL i Wl i+1 BL i Bl i+1 00 EPROM- Erasable PROM Drain Source Gate

6 Functional model of ROM Memory array Address register Column address decoder Line address decoder Transition amplifiers Transition logic Data register Data output Data input Refresh Logic Address Chip Select Simplified model Address decoder Memory array Transition logic Address Data

7 Behavioral test Address generator (Counter) Functioning ROM Testified ROM Comparison scheme Functioning/ Non- functioning Presupposes the existance of a functioning (golden) object (ROM).

8 Parity check All words must have even/odd number on 1-s. 01100 00011 1110 1 Parity bits Functional Testing It is not necessary to know how memory has been programmed (content of the memory).

9 Check sum. Memory ends with the sum of all memory words The number of memory words necessary for preserving the sum depends on the memory capacity Preserving part of the sum (newer/older) some information is lost. It is necessary to know a only where the check sum is preserved. It is not necessary to know the content of the memory.


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