1. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

2. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Visual Status 2 Rx_mac2buf I2C Fifo 31 TDCs TDC 0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

3. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Done: ◦ LM32 + WB-Crossbar + DPRAM + UART ◦ Soft-PLL FMC layout ◦ WR without PCI-express Currently: ◦ Deterministic PHY => First shot White Rabbit in KC705 ◦ Soft PLL (hardware + software). First goal: lock onto a 125 MHz xtal and phase shift under control of LM32 via UART To do (in order of priority): ◦ Endpoint (= MAC) <= Complex! <= under investigation ◦ Mini-nic <= Complex! ◦ Fabric redirector <= probably less complex ◦ PPS generator <= relatively straightforward ◦ 1-wire, SysCon <= easy? Status Listing 3

4. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology “The” LM32 system that everybody should use so there is one common viewpoint No TestDesign anymore => In SVN => CLBv2/trunk ◦ https://isvn.ific.uv.es/repos/KM3NeT/CLBv2/trunk/fw/CLBv 2_Design/lm32_2nd LM32_2 nd support for 16 wishbone slaves Added a “Date Revision ID register” wishbone device. ◦ Very handy to automatically track the firmware version that is in use. ◦ Generics “g_date_id” and “g_revision_id” are filled automatically by the (precision) synthesis script. ◦ When using ISE and XST someone needs to sort out how to pass generics in a scripted way. LM32_2nd 4

5. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Self Describing Bus ◦ Added descriptors “c_tdc_sdb” and “c_aes_tdc” readable at offset 0x1000 LM32_2nd 5 constant c_secbar_layout : t_sdb_record_array(15 downto 0) := (0 => f_sdb_embed_device(c_wrc_periph1_sdb, x"00000000"), -- UART 1 => f_sdb_embed_device(c_tdc_sdb, x"00000100"), -- TDCs 2 => f_sdb_embed_device(c_aes_sdb, x"00000200"), -- AES 3 => f_sdb_embed_device(c_wrc_periph4_sdb, x"00000300"), -- GPIO 4 => f_sdb_embed_device(c_wrc_periph5_sdb, x"00000400"), -- SPI 5 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000500"), -- I2C1 6 => f_sdb_embed_device(c_wrc_periph6_sdb, x"00000600"), -- I2C2 7 => f_sdb_embed_device(c_wrc_periph7_sdb, x"00000700"), -- Timer 8 => f_sdb_embed_device(c_wrc_periph8_sdb, x"00000800"), -- DATE_REVISION_ID 9 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000900"), 10 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000A00"), 11 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000B00"), 12 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000C00"), 13 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000D00"), 14 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000E00"), 15 => f_sdb_embed_device(c_wrc_periph3_sdb, x"00000F00") ); constant c_secbar_sdb_address : t_wishbone_address := x"00001000";

6. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Each owner of (sub)modules manages the top level module and a package describing the in and ouput types. For example, Genova manages: ◦ xwb_aes.vhd <= the top level AES module ◦ aes_pkg.vhd <= IO description LM32_2 nd TDC and AES 6 package aes_pkg is constant c_aes_word_size : integer := 64; type t_aes_in is record audio_in : std_logic; fifo_rd : std_logic; end record t_aes_in; type t_aes_out is record fifo_dout : std_logic_vector(c_aes_word_size-1 downto 0); fifo_full : std_logic; fifo_empty : std_logic; end record t_aes_out; end package aes_pkg; Doing so avoids changing entity “lm32_2 nd ”each time a sub module needs a small change…

7. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology In the current LM32_2 nd design for testing on the KC705 (…lm32_2nd\syn\syn_top\fpga.bit) there are “empty” placeholders for “xwb_aes” and “xwb_tdc”, because: 1.The TDC design should be moved in SVN to CLBv2/trunk in order to be able to link it relative when checking out trunk. 2.Both TDC and AES xwb modules should be slightly modified to incorporate the in- and output types ( t_aes_in, t_aes_out, t_tdc_in, t_tdc_out). (I already did this for AES but I need to commit the change to SVN) Valencia and Genova should add their design files to the scripts: LM32_2 nd TDC and AES 7

8. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology LM32_2 nd TDC and AES 8 # TDC # ### NOTE ### Valencia should place it's TDC files here (there is an empty placeholder for the time being) add_input_file -format VHDL -work work../../modules/tdc_pkg.vhd add_input_file -format VHDL -work work../../modules/xwb_tdc_empty.vhd # AES # ### NOTE ### Genova should place it's AES files here (there is an empty placeholder for the time being) add_input_file -format VHDL -work work../../modules/aes_pkg.vhd add_input_file -format VHDL -work work../../modules/xwb_aes_empty.vhd Precision => fpga-syn.tcl: Or XST => do_input_file_list.cmd: rem TDC rem ### NOTE ### Valencia should place it's TDC files here (there is an empty placeholder for the time being) @echo vhdl work "..\..\..\modules\tdc_pkg.vhd" >> %PrjFile% @echo ^ >> %XISEFile% @echo vhdl work "..\..\..\modules\xwb_tdc_empty.vhd" >> %PrjFile% @echo ^ >> %XISEFile% rem AES rem ### NOTE ### Genova should place it's AES files here (there is an empty placeholder for the time being) @echo vhdl work "..\..\..\modules\aes_pkg.vhd" >> %PrjFile% @echo ^ >> %XISEFile% @echo vhdl work "..\..\..\modules\xwb_aes_empty.vhd" >> %PrjFile% @echo ^ >> %XISEFile%

9. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology CLBv2/trunk/fw/CLBv2_Design/lm32_2 nd /to p contains: 1.A testbench “system.vhd” for simulation 2.“fpga.vhd” top design (basis for../syn/syn_top/fpga.bit) that is loadable on the KC705 where lm32_2 nd is running on 62.5 MHz. 3.THE top module “lm32_2 nd ” Why 62.5 MHz? ◦ Probably fast enough ◦ Lower power ◦ Easier to place&route LM32_2nd 9

10. July 10, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex PHY RXCDRLOCK_OUT is lost (at least in simulation) when data (i.e. non-idle) is received. ◦ Xilinx web case IRQ behaved different from SPEC reference design: ◦ Solved but not (yet) understood. Generic “g_divide_input_by_2” for “xwr_softpll_ng” in “wr_core.vhd” was not updated properly since the clock went from 125 to 62.5 MHz TX/RX packets (still) not active ◦ send ARP in simulation and inspect the endpoint details White Rabbit status 10