1. Digital System Ch2-1 Chapter 2 Boolean Algebra and Logic Gates Ping-Liang Lai ( 賴秉樑 ) Digital System 數位系統

2. Digital System Ch2-2 Outline 2.1Introduction 2.2Basic Definitions 2.3Axiomatic Definition of Boolean Algebra 2.4Basic Theorems and Properties of Boolean Algebra 2.5Boolean Functions 2.6Canonical and Standard Forms 2.7Other Logic Operations 2.8Digital Logic Gates 2.9Integrated Circuits

3. Digital System Ch2-3 2.1Introduction A set is collection of having the same property.  S: set, x and y: element or event  For example: S = {1, 2, 3, 4} » If x = 2, then x  S. » If y = 5, then y S. 在代數系統中，一個集合 S 的二元運算子 ( binary operator) 是 定義集合中的任何一對元素經此符號運算以後的結果，仍為 該集合中的一個元素。  For example: given a set S, consider a*b = c and * is a binary operator.  If (a, b) through * get c and a, b, c  S, then * is a binary operator of S.  On the other hand, if * is not a binary operator of S and a, b  S, then cS.

4. Digital System Ch2-4 2.2Boolean Algebra (Huntington, 1904) (p.52, 53) A set of elements S and two binary operators + and * 1.Closure: a set S is closed with respect to a binary operator if, for every pair of elements of S, the binary operator specifies a rule for obtaining a unique element of S.  x, y  S,  x+y  S » a+b = c, for any a, b, c  N. (“+” binary operator plus has closure) » But operator – is not closed for N, because 2-3 = -1 and 2, 3  N, but (-1)  N. 2.Associative law: a binary operator * on a set S is said to be associative whenever  (x * y) * z = x * (y * z) for all x, y, z  S » (x+y)+z = x+(y+z) 3.Commutative law: a binary operator * on a set S is said to be commutative whenever  x * y = y * x for all x, y  S » x+y = y+x

5. Digital System Ch2-5 Boolean Algebra (p.53) 4.Identity element: a set S is said to have an identity element with respect to a binary operation * on S if there exists an element e  S with the property that  e * x = x * e = x for every x  S » 0+x = x+0 =x for every x  I. I = {…, -3, -2, -1, 0, 1, 2, 3, …}. » 1*x = x*1 =x for every x  I. I = {…, -3, -2, -1, 0, 1, 2, 3, …}. 5.Inverse: a set having the identity element e with respect to the binary operator to have an inverse whenever, for every x  S, there exists an element y  S such that  x * y = e » The operator + over I, with e = 0, the inverse of an element a is (-a), since a+(-a) = 0. 6.Distributive law: if * and ． are two binary operators on a set S, * is said to be distributive over whenever ．  x * (y ． z) = (x * y) ． (x * z) Note  The associative law can be derived  No additive and multiplicative inverses  Complement 歷史 : 1854 年 George Boole 發展布林代數 ; 1904 E. V. Huntingtion 提出布林代數的假 設 ; 1938 年 C. E. Shannon 介紹一種二值布 林代數，稱為交換代數 (switch algebra) ， 說明了雙穩態的電子交換電路，可以用交 換代數來表示。

6. Digital System Ch2-6 Six Postulate of Huntington B = {0, 1} and two binary operations, + and ．  Closure: + and ． are closed.  + have identity 0, ． have identity 1 » x+0 =0+x = x » x ． 1 =1 ． x = x  + and ． are communication » x+y = y+x » x ． y =y ． x  Distribution » ． is distributive over whenever + − x+(y ． z) = xy+xz » + is distributive over whenever ． x − x ． (y+z) = (x+y) ． (x+z)  Each x  B,  x'  B (complement) s.t. » x  x' = 1 » x ． x' = 0  At least exist two element x, y  B and x ≠ y.

7. Digital System Ch2-7 2.3Postulates of Two-Valued Boolean Algebra (1/3) (p.55) B = {0, 1} and two binary operations, + and ． The rules of operations: AND 、 OR and NOT. 1.Closure (+ and ‧ ) 2.The identity elements (1) +: 0 (2) ． : 1 xy x．yx．y 000 010 100 111 xyx+y 000 011 101 111 x x'x' 01 10 ANDORNOT

8. Digital System Ch2-8 Postulates of Two-Valued Boolean Algebra (2/3) (p.56) 3.The commutative laws 4.The distributive laws xyzy+z x ． (y+z)x．yx．yx．zx．z(x ． y)+(x ． z) 00000000 00110000 01010000 01110000 10000000 10111011 11011101 11111111

9. Digital System Ch2-9 Postulates of Two-Valued Boolean Algebra (3/3) (p.56) 5.Complement  x+x'=1 → 0+0'=0+1=1; 1+1'=1+0=1  x ． x'=0 → 0 ． 0'=0 ． 1=0; 1 ． 1'=1 ． 0=0 6.Has two distinct elements 1 and 0, with 0 ≠ 1 Note  A set of two elements  + : OR operation; ． : AND operation  A complement operator: NOT operation  Binary logic is a two-valued Boolean algebra

10. Digital System Ch2-10 2.4Basic Theorems and Properties (p.57) Duality  The binary operators are interchanged; AND ( ． )  OR (+)  The identity elements are interchanged; 1  0

11. Digital System Ch2-11 Basic Theorems (1/3) (p.58) Theorem 1(a): x + x = x  x+x = (x+x) ． 1 by postulate: 2(b) = (x+x) ． (x+x')5(a) = x+xx'4(b) = x+05(b) = x2(a) Theorem 1(b): x ． x = x  x ． x = xx + 0 by postulate: 2(a) = xx + xx'5(b) = x ． (x + x')4(a) = x ． 15(a) = x2(b)

12. Digital System Ch2-12 Basic Theorems (2/3) (p.58) Theorem 2(a): x + 1 = 1  x + 1 = 1 ． (x + 1)postulate 2(b) =(x + x')(x + 1)5(a) = x + x' 14(b) = x + x' 2(b) = 15(a) Theorem 2(b): x ． 0 = 0by duality Theorem 3: (x')' = x  Postulate 5 defines the complement of x, x + x' = 1 and x x' = 0  The complement of x' is x is also (x')'

13. Digital System Ch2-13 Basic Theorems (3/3) (p.59) Theorem 6(a): x + xy = x  x + xy = x ． 1 + xypostulate2(b) = x (1 + y) 4(a) = x (y + 1)3(a) = x ． 12(a) = x2(b) Theorem 6(b): x (x + y) = xby duality By means of truth table (another way to proof ) xyxyx+xy 0000 0100 1001 1111

14. Digital System Ch2-14 DeMorgan's Theorems (p.59) DeMorgan's Theorems  (x+y)' = x' y'  (x y)' = x' + y' xyx + y(x + y)’x’y’x’y’ 0001111 0110100 1010010 1110000

15. Digital System Ch2-15 Operator Precedence (p.59) The operator precedence for evaluating Boolean Expression is  Parentheses ( 括弧 )  NOT  AND  OR Examples  x y' + z  (x y + z)'

16. Digital System Ch2-16 2.5Boolean Functions (p.60) A Boolean function  Binary variables  Binary operators OR and AND  Unary operator NOT  Parentheses Examples  F 1 = x y z'  F 2 = x + y'z  F 3 = x' y' z + x' y z + x y'  F 4 = x y' + x' z

17. Digital System Ch2-17 Boolean Functions (p.60) The truth table of 2 n entries Two Boolean expressions may specify the same function  F 3 = F 4 xyzF1F1 F2F2 F3F3 F4F4 0000000 0010111 0100000 0110011 1000111 1010111 1101100 1110100

18. Digital System Ch2-18 Boolean Functions (p.61) Implementation with logic gates  F 4 is more economical F 4 = x y' + x' z F 3 = x' y' z + x' y z + x y' F 2 = x + y'z

19. Digital System Ch2-19 Algebraic Manipulation (p.62) To minimize Boolean expressions  Literal: a primed or unprimed variable (an input to a gate)  Term: an implementation with a gate  The minimization of the number of literals and the number of terms → a circuit with less equipment  It is a hard problem (no specific rules to follow) Example 2.1 1.x(x'+y) = xx' + xy = 0+xy = xy 2.x+x'y = (x+x')(x+y) = 1 (x+y) = x+y 3.(x+y)(x+y') = x+xy+xy'+yy' = x(1+y+y') = x 4.xy + x'z + yz = xy + x'z + yz(x+x') = xy + x'z + yzx + yzx' = xy(1+z) + x'z(1+y) = xy +x'z 5.(x+y)(x'+z)(y+z) = (x+y)(x'+z), by duality from function 4. (consensus theorem with duality)

20. Digital System Ch2-20 Complement of a Function (p.63) An interchange of 0's for 1's and 1's for 0's in the value of F  By DeMorgan's theorem  (A+B+C)' = (A+X)'let B+C = X = A'X' by theorem 5(a) (DeMorgan's) = A'(B+C)'substitute B+C = X = A'(B'C') by theorem 5(a) (DeMorgan's) = A'B'C' by theorem 4(b) (associative) Generalizations: a function is obtained by interchanging AND and OR operators and complementing each literal.  (A+B+C+D+... +F)' = A'B'C'D'... F'  (ABCD... F)' = A'+ B'+C'+D'... +F'

21. Digital System Ch2-21 Examples (p.64) Example 2.2  F 1 ' = (x'yz' + x'y'z)' = (x'yz')' (x'y'z)' = (x+y'+z) (x+y+z')  F 2 ' = [x(y'z'+yz)]' = x' + (y'z'+yz)' = x' + (y'z')' (yz)‘ = x' + (y+z) (y'+z') = x' + yz‘+y'z Example 2.3: a simpler procedure  Take the dual of the function and complement each literal 1.F 1 = x'yz' + x'y'z. The dual of F 1 is (x'+y+z') (x'+y'+z). Complement each literal: (x+y'+z)(x+y+z') = F 1 ' 2.F 2 = x(y' z' + yz). The dual of F 2 is x+(y'+z') (y+z). Complement each literal: x'+(y+z)(y' +z') = F 2 '

22. Digital System Ch2-22 2.6Canonical and Standard Forms (p.64) Minterms and Maxterms A minterm (standard product): an AND term consists of all literals in their normal form or in their complement form.  For example, two binary variables x and y, » xy, xy', x'y, x'y'  It is also called a standard product.  n variables con be combined to form 2 n minterms. A maxterm (standard sums): an OR term  It is also call a standard sum.  2 n maxterms.

23. Digital System Ch2-23 Minterms and Maxterms (1/3) (p.65) Each maxterm is the complement of its corresponding minterm, and vice versa.

24. Digital System Ch2-24 Minterms and Maxterms (2/3) (p.65) An Boolean function can be expressed by  A truth table  Sum of minterms  f 1 = x'y'z + xy'z' + xyz = m 1 + m 4 +m 7 (Minterms)  f 2 = x'yz+ xy'z + xyz'+xyz = m 3 + m 5 +m 6 + m 7 (Minterms)

25. Digital System Ch2-25 Minterms and Maxterms (3/3) (p.66) The complement of a Boolean function  The minterms that produce a 0  f 1 ' = m 0 + m 2 +m 3 + m 5 + m 6 = x'y'z'+x'yz'+x'yz+xy'z+xyz'  f 1 = (f 1 ')' = (x+y+z)(x+y'+z) (x+y'+z') (x'+y+z')(x'+y'+z) = M 0 M 2 M 3 M 5 M 6  f 2 = (x+y+z)(x+y+z')(x+y'+z)(x'+y+z)=M 0 M 1 M 2 M 4 Any Boolean function can be expressed as  A sum of minterms (“sum” meaning the ORing of terms).  A product of maxterms (“product” meaning the ANDing of terms).  Both boolean functions are said to be in Canonical form.

26. Digital System Ch2-26 Sum of Minterms (p.66) Sum of minterms: there are 2 n minterms and 2 2n combinations of function with n Boolean variables. Example 2.4: express F = A+BC' as a sum of minterms.  F = A+B'C = A (B+B') + B'C = AB +AB' + B'C = AB(C+C') + AB'(C+C') + (A+A')B'C = ABC+ABC'+AB'C+AB'C'+A'B'C  F = A'B'C +AB'C' +AB'C+ABC'+ ABC = m 1 + m 4 +m 5 + m 6 + m 7  F(A, B, C) =  (1, 4, 5, 6, 7)  or, built the truth table first

27. Digital System Ch2-27 Product of Maxterms (p.68) Product of maxterms: using distributive law to expand.  x + yz = (x + y)(x + z) = (x+y+zz')(x+z+yy') = (x+y+z)(x+y+z')(x+y'+z) Example 2.5: express F = xy + x'z as a product of maxterms.  F = xy + x'z = (xy + x')(xy +z) = (x+x')(y+x')(x+z)(y+z) = (x'+y)(x+z)(y+z)  x'+y = x' + y + zz' = (x'+y+z)(x'+y+z')  F = (x+y+z)(x+y'+z)(x'+y+z)(x'+y+z') = M 0 M 2 M 4 M 5  F(x, y, z) =  (0, 2, 4, 5)

28. Digital System Ch2-28 Conversion between Canonical Forms (p.68) The complement of a function expressed as the sum of minterms equals the sum of minterms missing from the original function.  F(A, B, C) =  (1, 4, 5, 6, 7)  Thus, F'(A, B, C) =  (0, 2, 3)  By DeMorgan's theorem F(A, B, C) =  (0, 2, 3) F'(A, B, C) =  (1, 4, 5, 6, 7)  m j ' = M j  Sum of minterms = product of maxterms  Interchange the symbols  and  and list those numbers missing from the original form »  of 1's »  of 0's

29. Digital System Ch2-29 Example  F = xy + xz  F(x, y, z) =  (1, 3, 6, 7)  F(x, y, z) =  (0, 2, 4, 6)

30. Digital System Ch2-30 Standard Forms (P.70) Canonical forms are very seldom the ones with the least number of literals. Standard forms: the terms that form the function may obtain one, two, or any number of literals.  Sum of products: F 1 = y' + xy+ x'yz'  Product of sums: F 2 = x(y'+z)(x'+y+z')  F 3 = A'B'CD+ABC'D'

31. Digital System Ch2-31 Implementation (p.70, 71) Two-level implementation Multi-level implementation F 1 = y' + xy+ x'yz' F 2 = x(y'+z)(x'+y+z')

32. Digital System Ch2-32 2.7Other Logic Operations (p.71, 72) 2 n rows in the truth table of n binary variables. 2 2 n functions for n binary variables. 16 functions of two binary variables. All the new symbols except for the exclusive-OR symbol are not in common use by digital designers.

33. Digital System Ch2-33 Boolean Expressions (p.72)

34. Digital System Ch2-34 2.8Digital Logic Gates (p.73) Boolean expression: AND, OR and NOT operations Constructing gates of other logic operations  The feasibility and economy;  The possibility of extending gate's inputs;  The basic properties of the binary operations (commutative and associative);  The ability of the gate to implement Boolean functions.

35. Digital System Ch2-35 Standard Gates (p.73) Consider the 16 functions in Table 2.8 (slide 33)  Two are equal to a constant (F 0 and F 15 ).  Four are repeated twice (F 4, F 5, F 10 and F 11 ).  Inhibition (F 2 ) and implication (F 13 ) are not commutative or associative.  The other eight: complement (F 12 ), transfer (F 3 ), AND (F 1 ), OR (F 7 ), NAND (F 14 ), NOR (F 8 ), XOR (F 6 ), and equivalence (XNOR) (F 9 ) are used as standard gates.  Complement: inverter.  Transfer: buffer (increasing drive strength).  Equivalence: XNOR.

36. Digital System Ch2-36 Figure 2.5 Digital logic gates Summary of Logic Gates (p.74)

37. Digital System Ch2-37 Figure 2.5 Digital logic gates Summary of Logic Gates (p.74)

38. Digital System Ch2-38 Multiple Inputs (p.75) Extension to multiple inputs  A gate can be extended to multiple inputs. » If its binary operation is commutative and associative.  AND and OR are commutative and associative. » OR − x+y = y+x − (x+y)+z = x+(y+z) = x+y+z » AND − xy = yx − (x y)z = x(y z) = x y z

39. Digital System Ch2-39 Multiple Inputs (p.76)  NAND and NOR are commutative but not associative → they are not extendable. Figure 2.6 Demonstrating the nonassociativity of the NOR operator; (x ↓ y) ↓ z ≠ x ↓(y ↓ z)

40. Digital System Ch2-40 Multiple Inputs (p.76)  Multiple NOR = a complement of OR gate, Multiple NAND = a complement of AND.  The cascaded NAND operations = sum of products.  The cascaded NOR operations = product of sums. Figure 2.7 Multiple-input and cascated NOR and NAND gates

41. Digital System Ch2-41 Multiple Inputs (p.77)  The XOR and XNOR gates are commutative and associative.  Multiple-input XOR gates are uncommon?  XOR is an odd function: it is equal to 1 if the inputs variables have an odd number of 1's. Figure 2.8 3-input XOR gate

42. Digital System Ch2-42 Positive and Negative Logic (p.77) Positive and Negative Logic  Two signal values two logic values  Positive logic: H=1; L=0  Negative logic: H=0; L=1 Consider a TTL gate  A positive logic AND gate  A negative logic OR gate  The positive logic is used in this book Figure 2.9 Signal assignment and logic polarity

43. Digital System Ch2-43 Figure 2.10 Demonstration of positive and negative logic Positive and Negative Logic (p.78)

44. Digital System Ch2-44 2.9Integrated Circuits (p.79) Level of Integration An IC (a chip) Examples:  Small-scale Integration (SSI): < 10 gates  Medium-scale Integration (MSI): 10 ~ 100 gates  Large-scale Integration (LSI): 100 ~ xk gates  Very Large-scale Integration (VLSI): > xk gates VLSI  Small size (compact size)  Low cost  Low power consumption  High reliability  High speed

45. Digital System Ch2-45 Moore’s Law Transistors on lead microprocessors double every 2 years. (transistors on electronic component double every 18 months) source: http://www.intel.com

46. Digital System Ch2-46 Silicon Wafer and Dies Exponential cost decrease – technology basically the same:  A wafer is tested and chopped into dies that are packaged. Die ( 晶粒 ) Wafer ( 晶圓 ) AMD K8, source: http://www.amd.com dies along the edge

47. Digital System Ch2-47 Cost of an Integrated Circuit (IC) Today’s technology:   4.0, defect density 0.4 ~ 0.8 per cm 2 (A greater portion of the cost that varies between machines) (sensitive to die size) (# of dies along the edge)

48. Digital System Ch2-48 Examples of Cost of an IC Example 1: Find the number of dies per 30-cm wafer for a die that is 0.7 cm on a side.  The total die area is 0.49 cm 2. Thus Example 2: Find the die yield for dies that are 1 cm on a side and 0.7 cm on a side, assuming a defect density of 0.6 per cm 2.  The total die areas are 1 cm 2 and 0.49 cm 2. For the large die the yield is For the small die, it is

49. Digital System Ch2-49 Digital Logic Families (p.79) Digital logic families: circuit technology  TTL: transistor-transistor logic (dying?)  ECL: emitter-coupled logic (high speed, high power consumption)  MOS: metal-oxide semiconductor (NMOS, high density)  CMOS: complementary MOS (low power)  BiCMOS: high speed, high density

50. Digital System Ch2-50 Digital Logic Families (p.80) The characteristics of digital logic families  Fan-out: the number of standard loads that the output of a typical gate can drive.  Power dissipation.  Propagation delay: the average transition delay time for the signal to propagate from input to output.  Noise margin: the minimum of external noise voltage that caused an undesirable change in the circuit output.

51. Digital System Ch2-51 Fan-out (FO) The fan-out gates act as a load to the driving circuit because of their input capacitance C in  Therefore, the total input capacitance is (Figure 2.1(a))  In Figure 2.1(b), the external load capacitance C L is In Figure 2.2 where the total output capacitance is defined as Fig 2.1 Input capacitance and load effects Fig 2.2 Evolution of the inverter switching model (a) Single stage (b) Loading due to fan-out (a) External load (b) Complete switch model

52. Digital System Ch2-52 Delay Definitions V in V out Propagation delay

53. Digital System Ch2-53 Power Dissipation (1/2) The current I DD flowing from the power supply to ground gives a dissipated power of  Since V DD is assumed to be a constant  DC contribution Leakage current is very small, therefore, the value of P DC is thus quite small  However, leakage power on today is critical for low-power design. Where P DC is the DC term and P dyn is due to dynamic switching events. Where I DDQ is leakage current. Fig. DC current flow Fig. Origin of power dissipation calculation (a) VTC(b) DC current

54. Digital System Ch2-54 Power Dissipation (2/2) Dynamic power dissipation P dyn  P dyn arises from the observation that a complete cycle effectively creates a path for current to flow from the power supply to ground,  The average power dissipation over a single cycle with a period T is DC term dynamic power term Fig. Circuit for finding the transient power dissipation (a) Input voltage (b) Charge (c) Discharge

55. Digital System Ch2-55 CAD (p.80) CAD – Computer-Aided Design  Millions of transistors  Computer-based representation and aid  Automatic the design process  Design entry » Schematic capture » HDL – Hardware Description Language − Verilog, VHDL  Simulation  Physical realization » ASIC, FPGA, PLD

56. Digital System Ch2-56 Homework 2 Problem 2.1, 2.6, 2.8, 2.14, 2.20, 2.27, and 2.28 Due day: 10/16