1. VLSI-SoC 2001 IFIP - LIRMM Stream-based Arrays: Converging Design Flows for both, Reiner Hartenstein University of Kaiserslautern December 2- 4, 2001, Montpellier, France Reconfigurable and Hardwired....

2. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 2 >> Stream-based Computing Stream-based Computing Stream-based Compilation Techniques Use in Co-Design Now it’s up to You ! http://www.uni-kl.de

3. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 3 XPU family (IP cores): PACT Corp., Munich commercial rDPAs: rDPA (coarse grain) becoming important XPU128 **) bought ** flexible array: MorphICs CALISTO: Silicon Spice CS2000 family: Chameleon Systems MECA family: Malleable FIPSOC: SIDSA ACM: Quicksilver Tech CHESS array: Elixent MorphoSys: Morpho Tech http://pactcorp.com

4. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 4 array size: 10 x 16 = 160 rDPUs SNN filter Example: KressArray Family not used backbus connect KressArray Xplorer: rout thru only http://kressarray.de You may use it on your Netscape

5. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 5 Rapidly toward the Break-through replaceConcurrent Processes by more efficient parallelism: stream-based DPAs 1 **) reconfigurable 2 ) KressArray** [1995] and others [later] terms: DPU: datpath unit DPA: data path array rDPU: reconfigurable DPU rDPA: reconfigurable DPA Kress: a generalization of systolic array synthesis: stream-based r DPAs 2 ____ *) hardwired 1 ) systolic array* [1980] [ Broderson ] Bee Project chip-on-a-day* [2000] Generalization of the Systolic Array super systolic synthesis

6. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 6 compare Concurrent Computing DPU instruction sequencer DPU instruction sequencer DPU instruction sequencer DPU instruction sequencer.... Bus (es) or switch box CPU extremely inefficient massive bottleneck phenomena at run time control flow overhead instruction fetch / interpretation overhead address computation overhead - may be massive

7. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 7... with Stream-based Computing: (r) DPA for both, reconfigurable, and hardwired [ Brodersen ] DPU transport-triggered execution driven by data stream fr. / to memory or, fr. / to peripheral interface no instruction sequencer inside ! avoids run time overhead and bottleneck phenomena rDPA: drastically reduced reconfigurability overhead „instruction fetch“: at compile time

8. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 8 Soft rDPA ? Memory soft CPU miscellanous softDPUarraysoftDPUarray HLL Compiler 50 mio system gates soon even large rDPAs as soft IPs become feasible by >2005: don’t care about area efficiency ?

9. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 9 >> Stream-based Compilation Techniques Stream-based Computing Stream-based Compilation Techniques Use in Co-Design Now it’s up to You ! http://www.uni-kl.de

10. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 10 no routing! equations linear projection or algebraic mapping DPU architecture y + * x a placement Systolic Stream-based Computing System linear pipelines and uniform arrays only The Mathematician’s Synthesis Method Systolic Array [ H. T. Kung, 1980 ] : a DPA (Data Path Array) computing in space placement computing in time systolic arrays etc. and other transformations migration by re-timing this dichotomy is completely ignored by our CS curricula y 1 0  y 2 0 y 3 0 - - - y 1 y 2 y 3 - - - x 1 x 2 x 3 - - - data streams

11. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 11 2 General Stream-based Computing System heterogenous DPA or rDPA simulated annealing free form pipe network Mapper expression tree DPU architectures y + * x a simultaneous placement & routing 3 + ++ + * * * sh * xf - - 1 Scheduler data streams 4 2

12. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 12 an example by Nageldinger’s KressArray Xplorer Memory Communication Architecture … hot research topic in embedded systems storage context transformations [ Cathoor, Herz, Kougia, Soudris ] Synthesizable Memory Communication Architecture startups provide memory IPs or generators application not used Legend: sequencers memory ports Optimized Parallel Memory Controller GAG generic sequencer methodology available Herz

13. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 13 >> Use in Co-Design Stream-based Computing Stream-based Compilation Techniques Use in Co-Design Now it’s up to You ! http://www.uni-kl.de

14. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 14 data counter (s) program counter : state register Compiler Memory Datapath hardwired Sequencer Computer tightly coupled by compact instruction code “von Neumann” does not support soft data paths does not support soft data paths Datapath reconfigurable Xputer Scheduler Compiler Memory (multiple) sequencer Datapath Array University of Kaiserslautern loosely coupled by decision data bits only Xputer: The Soft Machine Paradigm reconfigurable Computer: the wrong Machine Paradigm “von Neumann” also for hardwired [ Broderson ] enabling technology published  10 years ago now a hot topic area full day course last week at Tampere, Finland

15. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 15 partitioning compiler high level programming language source Co-Compilation Analyzer / Profiler supporting different platforms Resource Parameters Xputer “Soft” Machine Paradigm Configware running on interface Reconfigurable Accelerators X-C compiler KressArray DPSS GNU C compiler X-C Partitioner Hardware / Software Co-Design turns to Configware / Software Co-Design Jürgen Becker’s Co-DE-X Co-Compiler [ASP-DAC’95] Computer Machine Paradigm Software running on  Processor

16. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 16 Loop Transformation Examples loop 1-8 body endloop loop 9-16 body endloop fork join strip mining loop 1-4 trigger endloop loop 1-2 trigger endloop loop 1-16 body endloop sequential processes: loop 1-8 trigger endloop reconf.array: host: resource parameter driven Co-Compilation loop 1-8 body endloop loop unrolling

17. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 17 >> Now it’s up to You ! Stream-based Computing Stream-based Compilation Techniques Use in Co-Design Now it’s up to You ! http://www.uni-kl.de

18. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 18 However, current CS Education …. Hardware invisible: under the surface … is based on the Submarine Model Brain usage: procedural-only Software Faculty Colleagues shy away from the Paradigm Shift: their Brain hurts? - can’t be: this Half has been amputated Algorithm Assembly Language procedural high level Programming Language Hardware Software This model disables...

19. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 19 Hardware, Configware... this model disables Hardware and Software as Alternatives Algorithm Software partitioning Software only Software & Hardw/Configw procedural structural Brain Usage: both Hemispheres Hardw/Configw only

20. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 20 The Dominance of the Submarine Model... Hardware... indicates, that our CS education system produces zillions of mentally disabled Persons (procedural) structurally disabled … completely disabled to cope with solutions other than software only It‘s time to attack the software faculty dictatorship. Get involved!

21. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 21 >>> thank you thank you for listening It’s up to You !

22. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 22 >>> END END

23. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 23 The Impact of Reconfigurable Logic Reconfigurable platforms bring a new dimension to digital system development and have a strong impact on SoC design. A rapidly growing large user base of HDL-savvy designers with FPGA experience. Flexibility promises spin-around times downto minutes instead of months for real time in-system debugging, profiling, verification, tuning, field-maintenance, and field upgrades A New Business Model (in-field debugging and upgrading... ) A Fundamental Paradigm Shift in Silicon Application Revenue / month Time / months Update 1 Product Update 2 11020 ASIC Product reconfigurable Product with download 30 [T. Kean]

24. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 24 The History of Paradigm Shifts “Mainstream Silicon Application is switching every 10 Years” TTL µproc., memory custom standard 1957 1967 1977 1987 1997 2007 Makimoto’s Wave ASICs, accel’s LSI, MSI ? ? “The Programmable System-on-a-Chip is the next wave“ reconfigurable Published in 1989

25. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 25 How’s next Wave ? 2007 custom standard 1957 1967 1977 1987 1997 procedural programming algorithm: variable resources: fixed Tredennick’s Paradigm Shifts hardwired algorithm: fixed resources: fixed 2007 FPGAs structural programming algorithm: variable resources: variable no further wave ! Coarse grain RAs Hartenstein’s Curve

26. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 26 The Impact of Makimoto’s Paradigm Shifts TTL µproc., memory custom standard ASICs, accel’s LSI, MSI reconfigurable 1957 1967 1977 1987 1997 2007 Procedural personalization via RAM-based Machine Paradigm structural personalization: RAM-based before run time Dr. Makimoto: FPL 2000 keynote Software Industry’s Secret of Success Configware Success Story by new Machine Paradigm

27. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 27 The History of Paradigm Shifts “Mainstream Silicon Application is switching every 10 Years” custom standard 1957 1967 1977 1987 1997 2007 Makimoto’s Wave TTL µproc., memory FPGAs ASICs, accel’s LSI, MSI coarse grain

28. © 2001, reiner@hartenstein.de http://www.fpl.uni-kl.de University of Kaiserslautern 28 KressArray Family generic Fabrics: a few examples Examples of 2 nd Level Interconnect: layouted over rDPU cell - no separate routing areas ! + rout-through and function rout- through only more NNports: rich Rout Resources Select Function Repertory select Nearest Neighbour (NN) Interconnect: an example 16328 24 4 2 rDPU Select mode, number, width of NNports Wired by Abutment