CIS3601 CIS 360: Introduction to Computer Systems Course Notes Wayne Heym Rick Parent

CIS3601 CIS 360: Introduction to Computer Systems Course Notes Wayne Heym (w.heym@ieee.org) http://www.cis.ohio-state.edu/~heym Rick Parent (parent@cis.ohio-state.edu) http://www.cis.ohio-state.edu/~parent Copyright © 1998-2003 by Rick Parent, Todd Whittaker, Bettina Bair, Pete Ware, Wayne Heym

CIS3602 Information Representation 1 u Positional Number Systems: position of character in string indicates a power of the base (radix). Common bases: 2, 8, 10, 16. (What base are we using to express the names of these bases?) –Base ten (decimal): digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 form the alphabet of the decimal system.  E.g., 316 10 = 3*100 + 1*10 + 6 *1 –Base eight (octal): digits 0, 1, 2, 3, 4, 5, 6, 7 form the alphabet.  E.g., 474 8 = 4*82 + 7*81 + 4*80 = 4*64+7*8+4*1

CIS3603 Information Representation 2 –Base 16 (hexadecimal): digits 0-9 and A-F.  E.g., 13C 16 = –Base 2 (binary): digits (called “bits”) 0, 1 form the alphabet.  E.g., 100110 = –In general, radix r representations use the first r chars in {0…9, A...Z} and have the form d n-1 d n-2 …d 1 d 0. Summing r n-1  d n-1 + r n-2  d n-2 + … + r 0  d 0 will convert to base 10. Why to base 10? 1*16 2 + 3*16 1 + 12*16 0 = 1*256+3*16+12*1 32 + 4 + 2

CIS3604 Information Representation 3 u Base Conversions –Convert to base 10 by multiplication of powers  E.g., 10012 5 = –Convert from base 10 by repeated division  E.g., 632 10 = ( ) 8 –Converting base x to base y: convert base x to base 10 then convert base 10 to base y 1*5 4 + 1*5 1 + 2*5 0 = 1*625 + 1*5 + 2 632/8 = 79 rmdr 0 79/8 = 9 rmdr 7 9/8 = 1 rmdr 1 1/8 = 0 rmdr 1 1170

CIS3605 Information Representation 4 –Special case: converting among binary, octal, and hexadecimal is easier t Go through the binary representation, grouping in sets of 3 or 4.  E.g., 11011001 2 = 11 011 001 = 331 8 11011001 2 = 1101 1001 = D9 16  E.g., C3B 16 = ( ) 8 1100 0011 1011 6 0 7 3

CIS3606 Information Representation 5 u What is special about binary? –The basic component of a computer system is a transistor (transfer resistor): a two state device which switches between logical “1” and “0” (actually represented as voltages on the range 5V to 0V). –Octal and hexadecimal are bases in powers of 2, and are used as a shorthand way of writing binary. A hexadecimal digit represents 4 bits, half of a byte. 1 byte = 8 bits. A bit is a binary digit. –Get comfortable converting among decimal, binary, octal, hexadecimal. Converting from decimal to hexadecimal (or binary) is easier going through octal.

CIS3607 Information Representation 6 BinaryHexDecimalBinaryHexDecimal 000000100088 000111100199 0010221010A10 0011331011B11 0100441100C12 0101551101D13 0110661110E14 0111771111F15

CIS3608 Information Representation 7 u Ranges of values –Q: Given k positions in base n, how many values can you represent? –A: n k values over the range (0…n k -1) 10 n=10, k=3: 10 3 =1000 range is (0…999) 10 n=2, k=8: 2 8 =256 range is (0…255) 10 n=16, k=4: 16 4 =65536 range is (0…65535) 10 –Q: How are negative numbers represented?

CIS3609 Information Representation 8 u Integer representation: –Value and representation are distinct. E.g., 12 may be represented as XII, C 16, 12 10, and 1100 2. Note: -12 may be represented as -C 16, -12 10, and -1100 2. –Simple and efficient use of hardware implies using a specific number of bits, e.g., a 32-bit string, in a binary encoding. Such an encoding is “fixed width.” –Four methods: (fixed-width) simple binary, signed magnitude, binary coded decimal, and 2’s complement. –Simple binary: as seen before, all numbers are assumed to be positive, e.g., 8-bit representation of 66 10 = 0100 0010 2 and 194 10 = 1100 0010 2

CIS36010 Information Representation 9 –Signed magnitude: simple binary with leading sign bit. 0 = positive, 1 = negative. E.g., 8-bit signed mag.: 66 10 = 0100 0010 2 -66 10 = 1100 0010 2 What ranges of numbers may be expressed in 8 bits? Largest: Smallest: Extend 1100 0010 to 12 bits: 0111 1111 1111 1000 0100 0010

CIS36011 Information Representation 10 Problems: (1) Compare the signed magnitude numbers 1000 0000 and 0000 0000. (2) Must have “subtraction” hardware in addition to “addition” hardware. –Binary Coded Decimal (BCD): use a 4 bit pattern to express each digit of a base 10 number 0000 = 0 0001 = 1 0010 = 2 0011 = 3 0100 = 4 0101 = 5 0110 = 6 0111 = 7 1000 = 8 1001 = 9 1010 = + 1011 = - E.g., 123 : 0000 0001 0010 0011 +123 : 1010 0001 0010 0011 -123 : 1011 0001 0010 0011

CIS36012 Information Representation 11 BCD Disadvantages: –Takes more memory. 32 bit simple binary can represent more than 4 billion discrete values. 32 bit BCD can hold a sign and 7 digits (or 8 digits for unsigned values) for a maximum of 110 million values, a 97% reduction. –More difficult to do arithmetic. Essentially, we must force the Base 2 computer to do Base 10 arithmetic. BCD Advantages: –Used in business machines and languages, i.e., in COBOL for precise decimal math. –Can have arrays of BCD numbers for essentially arbitrary precision arithmetic.

CIS36013 Information Representation 12 –Two’s Complement t Used by most machines and languages to represent integers. Fixes the -0 in the signed magnitude, and simplifies machine hardware arithmetic. t Divides bit patterns into a positive half and a negative half (with zero considered positive); n bits creates a range of [-2 n-1 … 2 n-1 -1]. CODE 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Simple 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Signed +0 1 2 3 4 5 6 7 -0 -2 -3 -4 -5 -6 -7 2’s comp 0 1 2 3 4 5 6 7 -8 -7 -6 -5 -4 -3 -2

CIS36014 Information Representation 12 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 -0 -2 -3 -4 -5 -6 -7 7 6 5 4 3 2 1 0 -2 -3 -4 -5 -6 -7 -8 Simple binary Sign-magnitude 2’s complement

CIS36015 Information Representation 13 –Representation in 2’s complement; i.e., represent i in n-bit 2’s complement, where -2 n-1  i  +2 n-1 -1 t Nonnegative numbers: same as simple binary t Negative numbers: –Obtain the n-bit simple binary equivalent of | i | –Obtain its negation as follows: Invert the bits of that representation Add 1 to the result t Ex.: convert -320 10 to 16-bit 2’s complement t Ex.: extend the 12-bit 2’s complement number 1101 0111 1000 to 16 bits. 320 = 00000001 01000000 - 00000001 01000000 = 1111110 10111111 + 1 -320 = 11111110 11000000 = 0xFEC0 1111 1101 0111 1000 = 0xFD78

CIS36016 Information Representation 14 u Binary Arithmetic –Addition and subtraction only for now –Rules: similar to standard addition and subtraction, but only working with 0 and 1. t 0 + 0 = 00 - 0 = 0 t 1 + 0 = 11 - 0 = 1 t 1 + 1 = 101 - 1 = 0 –Must be aware of possible overflow.  Ex.: 8-bit signed magnitude 0101 0110 + 0110 0011 =  Ex.: 8-bit signed magnitude 0101 0110 - 0110 0011 =

CIS36017 Information Representation 15 u 2’s Complement binary arithmetic –Addition and subtraction are the same operation –Still must be aware of overflow.  Ex.: 8 bit 2’s complement: 23 10 + 45 10 =  Ex.: 8 bit 2’s complement: 100 10 + 45 10 =  Ex.: 8 bit 2’s complement: 23 10 - 45 10 =

CIS36018 Information Representation 16 –2’s Complement overflow t Opposite signs on operands can’t overflow t If operand signs are same, but result’s sign is different, must have overflow t Can two positives sum to positive and still have overflow? Can two negatives?

CIS36019 Information Representation 17 u Characters and Strings –EBCDIC, Extended Binary Coded Decimal Interchange Code t Used by IBM in mainframes (360 architecture and descendants). t Earliest system –ASCII, American Standard Code for Information Interchange. t Most common system –Unicode, http://www.unicode.org t New international standard t Variable length encoding scheme with either 8- or 16-bit minimum t “a unique number for every character, no matter what the platform, no matter what the program, no matter what the language.”

CIS36020 Information Representation 18 u ASCII –see table 1.7 on pg. 18. t In Unix, run “man ascii”. –7 bit code t Printable characters for human interactions t Control characters for non-human communication (computer- computer, computer-peripheral, etc.) –8-bit code: most significant bit may be set t Extended ASCII (IBM), includes graphical symbols and lines t ISO 8859, several international standards t Unicode’s UTF-8, variable length code with 8-bit minimum

CIS36021 ASCII u Easy to decode –takes up a predictable amount of space u Upper and lower case characters are 0x20 (32 10 ) apart u ASCII representation of ‘3’ is not the same as the binary representation of 3. –To convert ASCII to binary (an integer), ‘3’-’0’ = 3 u Line feed (LF) character –000 1010 2 = 0x0a= 10 10

CIS36022 Information Representation 19 u String: definition is programming language dependent. –C, C++: strings are arrays of characters terminated by a null byte. u Parity: Simple error detection –Data transmission, aging media, static interference, dust on media, etc. demand the ability to detect errors. –Single bit errors detected by using parity checking.

CIS36023 Information Representation 20 –How to detect a 1-bit error:  Ex.: send ASCII ‘S’ : send 1010011, but receive 1010010 ? t Add a 1-bit parity to make an odd or even number of bits per byte. t Parity bit is stripped by hardware after checking. Sender/receiver both agree to odd or even parity. t 2 flipped bits in the same encoding are not detected.

CIS36024 Information Representation 21 u Two meanings for Hamming distance. 2 nd is generalization of 1 st. 1 st is: distance between two encodings of the same length. 1.A count of the number of bits different in encoding 1 vs. encoding 2. E.g.,dist(1100, 1001) = dist(0101, 1101) = 2.Generalize to an entire code by taking the minimum over all distinct pairs (2 nd meaning). –The ASCII encoding scheme has a Hamming distance of 1. –A simple parity encoding scheme has a Hamming distance of 2. u Hamming distance serves as a measure of the robustness of error checking (as a measure of the redundancy of the encoding).

CIS36025 Information Representation u Simple data compression –ASCII codes are fixed length. –Huffman codes are variable length and based on statistics of the data to be transmitted. t Assign the shortest encoding to the most common character. –In English, the letter ‘e’ is the most common. –Either establish a Huffman code for an entire class of messages, –Or create a new Huffman code for each message, sending/storing both the coding scheme and the message. t “a widely used and very effective technique for compressing data; savings of 20% to 90% are typical, depending on the characteristics of the file being compressed.” (Cormen, p. 337)

CIS36026 Information Representation 22 t Huffman Tree for “a man a plan a canal panama” –Examine data set and determine frequencies of letters (example ignores spaces, normally significant) –Create a forest of single node trees. Choose the two trees having the smallest total frequencies (the two “smallest” trees), and merge them together (lesser frequency as the left subtree, for definiteness, to make grading easier). Continue merging until only one tree remains.

CIS36027 Information Representation 23 Huffman Tree for "a man a plan a canal panama" 'a'.4762 'n'.1905 'c'.0476 'l'.0952.1428 'm'.0952 'p'.0952.1905.3333.5238 1.0 u Reading a ‘1’ calls for following the left branch. u Reading a ‘0’ calls for following the right branch. u Decoding using the tree: To decode ‘0001’, start at root and follow r_child, r_child, r_child, l_child, revealing encoded ‘m’.

CIS36028 Information Representation 24 t Comparison of Huffman and 3-bit code example –3-bit: 000 011000100 000 101010000100 000 001000100000010 101000100000011000 = 63 bits –Huffman: 1 0001101 1 00000010101 1 001110110010 0000101100011 = 46 bits –Savings of 17 bits, or 27% of original message

CIS36029 ISEM FAQ 1 u Editing, Assembling, Linking, and Loading –There are three components to the Instructional SPARC Emulator (ISEM) package that we use for this class: t the assembler, t the linker, and t the emulator/debugger.

CIS36030 TERMS u Bit u Byte u Halfword u Word u Doubleword u Kilobyte (KB) u Megabyte (MB) u Gigabyte (GB) u Second (s) u Millisecond (ms)  Microsecond (  s) u Nanosecond (ns) u Picosecond (ps) u Hetz (Hz) u Kilohertz (kHz) u Megahertz (MHz) u 100 megahertz = ? Clock period 10 ns

CIS36031 ISEM FAQ 2 u Editing –There are a number of programs that you can use to create your source files. t Emacs is probably the most popular,; t vi is also available, but its command syntax is difficult to learn and use; t using pine program, you can use the pico editor, which combines many features of Emacs into a simple menu-driven facility –Start Emacs by “xemacs sourcefile.s &”, which creates the file called sourcefile.s. –Use the tutorial, accessed by typing "Ctrl-H Ctrl-H t". –For other editors, you are on your own.

CIS36032 Example Sparc Assembly Language Instructions % type xmp0.s.data ! Assembler directive: data starts here. A_s, B_s, and A_s:.word ’?’ ! C_s are symbolic constants. Furthermore, each B_s :.word 0x30 ! is an address of a certain-sized chunk of memory. Here, C_s :.word 0 ! each chunk is four bytes (one word) long. When the ! program gets loaded, each of these chunks stores a ! number in 2’s complement encoding, as follows: At ! address C_s, zero; at B_s, 48; at A_s, 0x3F = 077 = 63..text! Assembler directive, instructions start here start:! Label (symbolic constant) for this address set A_s, %r2! Put address A_s into register 2 ld [%r2], %r2! Use r2 as an indirect address for a load (read) set B_s, %r3! Put address B_s into register 3 ld [%r3], %r3! Read from B_s and replace r3 w/ value at addr B_s sub %r2, %r3, %r2! Subtract r3 from r2, save in r2 set C_s, %r4! Put address C_s into register 4 st %r2, [%r4]! Store (write) r2 to memory at address C_s terminate:! Label for address where ’ta 0’ instruction stored ta 0! Stop the program beyond_end:! Label for address beyond the end of this program

CIS36033 ISEM FAQ 3 u Assembling –The assembler is called "isem-as", and is the GNU Assembler (GAS), configured to cross-assemble to a SPARC object format. –It is used to take your source code, and produce object code that may be linked and run on the ISEM emulator. –The syntax for invoking the assembler is: isem-as [-a[ls]] sourcefile.s -o objectfile.o –The input is read from sourcefile.s, and the output is written to objectfile.o. –The option "-a" tells the assembler to produce a listing file. The sub-options "l" and "s" tell the assembler to include the assembly source in the listing file and produce a symbol table, respectively.

CIS36034 ISEM FAQ 4 u The listing file –Will identify all the syntactic errors in your program, and it will warn you if it identifies "suspicious" behavior in your source file. –Column 1 identifies a line number in your source file. –Column 2 is an offset for where this instruction or data resides in memory. –Column 3 is the image of what is put in memory, either the machine instructions or the representation of the data. –The final column is the source code that produced the line. –At the bottom of the file you will find the symbol table. –Again, the symbols are represented as offsets that are relocated when the program is loaded into memory.

CIS36035 isem-as -als labn.s -o labn.o >! labn.lst 1.data 2 0030 0000003F A_s:.word ’?’ 3 0034 00000030 B_s:.word 0x30 4 0038 00000000 C_s:.word 0 5.text 6 start: 7 0000 05000000 set A_s, %r2 7 8410A000 8 0008 C4008000 ld [%r2], %r2 9 000c 07000000 set B_s, %r3 9 8610E000 10 0014 C600C000 ld [%r3], %r3 11 0018 84208003 sub %r2, %r3, %r2 12 001c 09000000 set C_s, %r4 12 88112000 13 0024 C4210000 st %r2, [%r4] 14 terminate: 15 0028 91D02000 ta 0 16 002c 00000000 beyond_end: DEFINED SYMBOLS xmp0.s:2 2:00000030 A_s xmp0.s:3 2:00000034 B_s xmp0.s:4 2:00000038 C_s xmp0.s:6 1:00000000 start xmp0.s:14 1:00000028 terminate xmp0.s:16 1:0000002c beyond_end UNDEFINED SYMBOLS Line in source file (.s) Offset to address in memory Contents at address in memory Labels are symbolic offsets

CIS36036 ISEM FAQ 5 u Linking –Linking turns a set of raw object file(s) into an executable program. –From the manual page, "ld combines a number of object and archive files, relocates their data and ties up symbol references. Often the last step in building a new compiled program to run is a call to ld." –Several object files are combined into one executable using ld; the separate files could reference symbols from one another. –The output of the linker is an executable program. –The syntax for the linker is as follows: isem-ld objectfile.o [-o execfile] Examples % isem-ld foo.o -o foo Links foo.o into the executable foo. % isem-ld foo.o Links foo.o into the executable a.out.

CIS36037 ISEM FAQ 6 u Loading/Running –Execute the program and test it in the emulation environment. –The program "isem" is used to do this, and the majority of its features are covered in your lab manual. –Invoke isem as follows isem [execfile] Examples % isem foo Invokes the emulator, loads the program foo % isem Invokes the emulator, no program is loaded –Once you are in the emulator, you can run your program by typing "run" at the prompt.

CIS36038 ISEM Debugging Tools 1 % isem xmp0 Instructional SPARC Emulator Copyright 1993 - Computer Science Department University of New Mexico ISEM comes with ABSOLUTELY NO WARRANTY ISEM Ver 1.00d : Mon Jul 27 16:29:45 EDT 1998 Loading File: xmp0 2000 bytes loaded into Text region at address 8:0 2000 bytes loaded into Data region at address a:2000 PC: 08:00000020 nPC: 00000024 PSR: 0000003e N:0 Z:0 V:0 C:0 start : sethi 0x8, %g2 ISEM> run Program exited normally. Assembly language programs are not notoriously chatty.

CIS36039 ISEM Debugging Tools 2 u reg –Gives values of all 32 general registers –Also PC u symb –Shows the resolved values of all symbolic constants u dump [addr] –Either symbol or hex address –Gives the values stored in memory ISEM> reg ----0--- ----1--- ----2--- ----3--- ----4--- ----5--- ----6--- ----7--- G 00000000 00000000 0000000f 00000030 00002068 00000000 00000000 00000000 O 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 L 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 I 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 PC: 08:0000004c nPC: 00000050 PSR: 0000003e N:0 Z:0 V:0 C:0 beyond_end : unimp ISEM> symb Symbol List A_s : 00002060 B_s : 00002064 C_s : 00002068 beyond_end : 0000004c start : 00000020 terminate : 00000048 ISEM> dump A_s 0a:00002060 00 00 00 3f 00 00 00 30 00 00 00 0f 00 00 00 00...?...0........ 0a:00002070 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00................ 0a:00002080 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00................

CIS36040 ISEM Debugging Tools 3 u break [addr] –Set breakpoints in execution –Once execution is stopped, you can look at the contents of registers and memory. u trace –Causes one (or more) instruction(s) to be executed –Registers are displayed –Handy for sneaking up on an error when you’re not sure where it is. u For the all-time “most wanted” list of errors (and their fixes) –http://www.cis.ohio-state.edu/~heym/360/common/faq.html

CIS36041 Basic Components 1 u Terminology from Ch. 2: –Flip flop: basic storage device that holds 1 bit –D flip flop: special flip flop that outputs the last value that was input to it (a data signal). –Clock: two different meanings: (1) a control signal that oscillates (low to high voltage) every x nanoseconds; (2) the “write select” line for a flip flop.

CIS36042 Basic Components 2 –Register: collection of flip flops with parallel load. Clock (or “write select”) signal controlled. Stores instructions, addresses, operands, etc. –Bus: Collection of related data lines (wires).

CIS36043 Basic Components 3 –Combinational circuits: implement Boolean functions. No feedback in the circuit, output is strictly a function of input. t Gates: and, or, not, xor E.g., xy +  z

CIS36044 Basic Components 4 –Gates can be used in combination to implement a simple (half) adder. t Addition creates a value, plus a carry-out. Z = X  Y CO = X  Y X Y Z CO

CIS36045 Basic Components 5 –Sequential Circuits: introduce feedback into the circuit. Outputs are functions of input and current state. –Multiplexers: combinational circuits that use n bits to select an output from 2 n input lines. D C Q

CIS36046 Basic Components 6 u Von Neumann Architecture –Can access either instructions or data from memory in each cycle. –One path to memory (von Neumann bottleneck) –Stored program system. No distinction between programs and data

CIS36047 Basic Components 7 Examples of Von Neumann architecture to be explored in this course: u SAM: tiny, good for learning architecture u MIPS: text’s example assembly language u SPARC: labs Roughly, the order of presentation in this course is as follows: u A couple of days on the Main Memory System u Weeks on the Central Processing Unit (CPU) u Finish the course with the I/O System

CIS36048 Basic Components 8 u Memory: Can be viewed as an array of storage elements. –The index of each element is called the address. –Each element holds the same number of bits. How many bits per element? 8, 16, 32, 64?

CIS36049 Memory Element & Address Sizes If a machine’s memory is 5-bit addressable, then, at each distinct address, 5 bits are stored. The contents at each address are represented by 5 bits. If 3 bits are used to represent memory addresses, then the memory can have at most 2 3 = 8 distinct addresses. Such a memory can store at most 8  5 = 40 bits of data. If the data bus is 10 bits wide, then up to 10 bits at a time can be transferred between memory and processor; this is a 10-bit word. Address Contents DecimalBinary 000000011 100101111 201001110 301110100 410000101 510101110 611010100 711110011

CIS36050 Basic Components 9 u Let’s look deeper. –Suppose each memory element is stored in a bank and given a relative address. –You could have several such banks in your memory. –The GLOBAL address of each element would be: [relative address] & [bank address]. –To get two elements at a time, start reading from bank 0 (don’t start from bank 1; this would be a “memory address not aligned” error). 000 001 010 011 100 101 Bank 0 000 001 010 011 100 101 Bank 0 000 001 010 011 100 101 Bank 1 000 0 001 0 010 0 011 0 100 0 101 0 000 1 001 1 010 1 011 1 100 1 101 1 Global addresses, not contents. Think of the contents as being underneath the global addresses.

CIS36051 Basic Components 10 –Memory alignment: Assume a byte addressable machine with 4-byte words. Where are operands of various sizes positioned? t bytes: on a byte boundary (any address) t half words: on half word boundary (even addresses) t words: on word boundary (addresses divisible by 4) t double words: on double word boundary (addresses divisible by 8)

CIS36052 Basic Components 11 u Byte ordering: how data is stored in memory t big-endian: High order (big end) is at byte 0. t little-endian: Low order (little end) is at byte 0. –Ex.: 247896511 10 = 0EC699BF 16

CIS36053 Basic Components 12 u Read/Write operations: must know the address to read or write. (read = fetch = load, write = store) t CPU puts address on address bus t CPU sends read signal –(R/  W=1, CS=1) –(Read/don’t Write, Chip Select) t Wait t Memory puts data on data bus –reset (CS=0) D0 D1 D(n-1) A0 A1 A(m-1) CS R/  W

CIS36054 Basic Components 13 –Types of memory: t ROM: Read Only Memory: non-volatile (doesn’t get erased when powered down; it’s a combinational circuit!) t PROM: Programmable ROM: use a ROM burner to write data to it initially. Can’t be re-written. t EPROM: Erasable PROM. Uses UV light to erase. t EEPROM: Electrically Erasable PROM. t RAM: Random access memory. Can efficiently read/write any location (unlike sequential access memory). Used for main memory. –Many variations (types) of RAM, all volatile SDRAM, DDR SDRAM RDRAM www.tomshardware.com

CIS36055 Basic Components 14 u CPU: executes instructions -- primitive operations that the computer can perform. –E.g.,arithmeticA+B data movementA := B controlif expr goto label logicalAND, OR, XOR… t Instructions specify both the operation and the operands. Operands are usually locations in memory where the actual operands may be found (addresses of actual operands).

CIS36056 Basic Components 15 –Instruction set: all instructions for a machine. Instruction format specifies number and type of operands. t Ex.: Could have an instruction like ADD A, B, R Where A, B, and R are the addresses of operands in memory. The result is R := A+B.

CIS36057 Basic Components 16 –Actually, the “instruction” might be represented in a source file as: 0x41444420412C20422C20520A. … A D D A, B, R As such, it is an assembly language instruction. –An assembler might translate it to, say, 0x504C, the machine’s representation of the instruction. As such, it is a machine language instruction.

CIS36058 A Simple Instruction Set 1 u Simple instruction set: the Accumulator machine. –Simplify instruction set by only allowing one operand. Accumulator implied to be the second operand. –Accumulator is a special register. Similar to a simple calculator.  ADD addrACC  ACC + M[addr]  SUB addrACC  ACC - M[addr]  MPY addrACC  ACC * M[addr]  DIV addrACC  ACC / M[addr]  LOAD addrACC  M[addr]  STORE addrM[addr]  ACC

CIS36059 A Simple Instruction Set 2  Ex.: C = A  B + C  D LOAD 20! 1)Acc<-M[20] MPY 21! 2)Acc<-Acc*M[21] STORE 30! M[30]<-Acc LOAD 22! 3)Acc<-M[22] MPY 23! 4)Acc<-Acc*M[23] ADD 30! 5)Acc<-Acc+M[30] STORE 22! M[22]<-Acc –Machine language: Converting from assembly language to machine language is called assembling. Accumulator 1) 2) 3) 4) 5)

CIS36060 A Simple Instruction Set 3 t Assume 8-bit architecture. Each instruction may be 8 bits. 3 bits hold the op-code and 5 bits hold the operand. t How much memory can we address? t How many op-codes can we have? t Convert the mnemonic op-codes into binary codes.

CIS36061 A Simple Instruction Set 4 t Hand assemble our program: LOAD 20100 10100 MPY 21010 10101 STORE 30101 11110... t Instructions are stored in consecutive memory:

CIS36062 A Simple Instruction Set 5

CIS36063 A Simple Instruction Set 6 –Control signals: control functional units to determine order of operations, access to bus, loading of registers, etc..

CIS36064 A Simple Instruction Set 7 0 1 2 3 State Y N 4 5 Y N 7 8 6

CIS36065 State 0: Control Signals 2, 5, 9, 3 Put the address of the next instruction in the Addr Register and Inc. PC.

CIS36066 State 1: Control Signals 13, 14 Fetch the word of memory at Address, and load into Data Register.

CIS36067 State 2: Control Signals 6, 4 Send the word from the Data Register to the Instruction Register.

CIS36068 State 3: Control Signals 12, 5 Put the address from the instruction in the Address Register.

CIS36069 After State 3, what values are now stored in each register? u PC u MAR u MDR u IR u ACC

CIS36070 State 4: Control Signals 0, 7 Take the value from the ACCumulator and store it in the Data Register.

CIS36071 State 5: Control Signal 13 Write the data from the Data Register to the address stored in the MAR.

CIS36072 State 6: Control Signals 13, 14 Load the word at the Address from the Addr Reg into the Data Register.

CIS36073 After State 6, what values are now stored in each register? u PC u MAR u MDR u IR u ACC

CIS36074 State 7: Control Signals 6, 1 Load the word from Data Register into the ACCumulator.

CIS36075 State 8: Control Signals 6, 8, 10/11, 1 Use word from the Data Register for Arith Op and put result in ACC.

CIS36076 New Instruction What is necessary to implement a new instruction? New states? New control signals? New fetch/execute cycle? An Example: SWAP Exchange value in Accumulator with value at Address SWAP addr ! Acc <- #M[addr], M[addr] <- #Acc

CIS36077 New Instruction u What changes to fetch/execute cycle? –The fetch part of the cycle usually remains the same. –Recall the values stored in registers after each state t E.g., After State 6, t what values are in each register? –PC –MAR –MDR –IR –ACC t Handy to have M[addr] in MDR –Start after state 6 then….

CIS36078 New State 9: Control Signals 6, 5 Save the Data value from the MDR in the Address Register. MDR -> bus Load MAR

CIS36079 New State 10: Control Signals 0, 7 Send the ACCumulator value to the Data Register. ACC -> bus load MDR

CIS36080 New State 11: Control Signals ?, 1 Put the saved value from the MAR into the ACCumulator. MAR->bus load ACC Note: there is no control signal in the current architecture opposite of 5 (Load MAR), so we would have to create a new control signal (MAR to bus) in addition to creating these new states.

CIS36081 New State 12 (Old 3): Control Signals 12, 5 Put (reload) the address from the instruction in the Address Register. Addr -> bus load MAR

CIS36082 New State 13 (Old 5): Control Signals 13 Write the data from the Data Register to the address stored in the MAR. CS

CIS36083 New Instruction Example Summary u Changes to States, added 9 thru 13 u Changes to Signals, added 15: MAR -> bus u Changes to Fetch/Execute, new register transfer language (RTL) PC -> bus, load MAR, INC PC, Load PC CS, R/w MDR -> bus, load IR Addr -> bus, load MAR CS, R/w MDR -> bus, load MAR ACC -> bus, load MDR MAR -> bus, load ACC Addr -> bus, load MAR CS

CIS36084 Hardware Control Signals XXX counter 101 0110 Opcode = 101 And Clock = 0110 clock IR Open gates, CS, etc.

CIS36085 Instruction Set Architectures 1 u RISC vs. CISC –Complex Instruction Set Computer (CISC): many, powerful instructions. Grew out of the need for high code density. Instructions have varying lengths, number of operands, formats, and clock cycles in execution. –Reduced Instruction Set Computer (RISC): fewer, less powerful, optimized instructions. Grew out of need for speed. Instructions have fixed length, number of operands, formats, and similar number of clock cycles in execution.

CIS36086 Instruction Set Architectures 2 u Motivation: memory is comparatively slow. –10x to 20x slower than processor. –Need to minimize number of trips to memory. t Provide faster storage in the processor -- registers. t Registers (16, 32, 64 bits wide) are used for intermediate storage for calculations, or repeated operands. t Accumulator machine –One data register -- ACC. –2 memory accesses per instruction -- one for the instruction and one for the operand. t Add more registers (R0, R1, R2, …, Rn)

CIS36087 Instruction Set Architectures 3 u How many addresses to specify? –With binary operations, need to know two source operands, a destination, and the operation.  E.g., op (dest_operand) (src_op1) (src_op2) –Based on number of operands, could have: t 3 addr. machine: both sources and dest are named. t 2 addr. machine: both sources named, dest is a source. t 1 addr. machine: one source named, other source and dest. is the accumulator. t 0 addr. machine: all operands implicit and available on the stack.

CIS36088 Instruction Set Architectures 4  1-address architecture: a:=a  b+c  d  e –Memory onlyUsing registers t 1½-address architecture: one operand must always be a register. (½ address is register, 1 address is the memory operand: LOAD 100, R1). –Like an accumulator machine, but with many accumulators.

CIS36089 Instruction Set Architectures 5  3-address architecture: a:=a  b+c  d  e –Using memory only: –Using registers: –What about instruction size?

CIS36090 Instruction Set Architectures 6  2-address architecture: a:=a  b+c  d  e –Using memory only: –Using registers: –Most CISC arch. this way, making 1 operand implicit

CIS36091 Instruction Set Architectures 7  0-address architecture: a:=a  b+c  d  e –Stack machine: All operands are implicit. Only push and pop touch memory. All other operands are pulled from the top of stack, and result is pushed on top. E.g., HP calculators.

CIS36092 Instruction Set Architectures 8 u Load/Store Architectures -- RISC –Use of registers is simple and efficient. Therefore, the only instructions that can access memory are load and store. All others reference registers.

CIS36093 Instruction Set Architectures 9 u Why load/store architectures? –Number of instructions (hence, memory references to fetch them) is high, but can work without waiting on memory. –Claim: overall execution time is lower. Why? t Clock cycle time is lower (no micro code interpretation). t More room in CPU for registers and memory cache. t Easier to overlap instruction execution through pipelining. –Side effects: t Register interlock: delaying execution until memory read completes. t Instruction scheduling: rearranging instructions to prevent register interlock (loads on SPARC) and to avoid wasting the results of pipelined execution (branches on SPARC).

CIS36094 SPARC Assembly Language 1 u SPARC (Scalable Processor ARChitecture) –Used in Sun workstations, descended from RISC-II developed at UC Berkeley –General Characteristics: t 32-bit word size (integer, address, register size, etc.) t Byte-addressable memory t RISC load/store architecture, 32-bit instruction, few addressing modes t Many registers (32 general purpose, 32 floating point, various special purpose registers) –ISEM: Instructional SPARC Emulator - nicer than a real machine for learning to write assembly language programs.

CIS36095 SPARC Assembly Language 2 u Structure –Line oriented: 4 types of lines t Blank - Ignored t Labeled - –Any line may be labeled. Creates a symbol in listing. Labels must begin with a letter (other than ‘L’), then any alphanumeric characters. Label must end with a colon “ : ”. Label just assigns a name to an address.  Assembler Directives - E.g.,.data.word.text, etc. t Instructions –Comments start after “ ! ” character and go to the end of the line..data x:.word 0x42 y:.word 0x20 z:.word 0.text start: set x, %r2 ld [%r2], %r2 set y,%r3 ld [%r3], %r3 ! Load [x] into reg 2 ! Load [y] into reg 3

CIS36096 SPARC Assembly Language 3 u Directives: Instructions to the assembler –Not executed by the machine .data -- following section contains declarations –Each declaration reserves and initializes a certain number of bits of storage for each of zero or more operands in the declaration..word -- 32 bits.half -- 16 bits.byte -- 8 bits E.g.,.data w:.half 27000 x:.byte 8 y:.byte ’m’, 0x6e, 0x0, 0, 0 z:.word 0x3C5F .text -- following section contains executable instructions

CIS36097 SPARC Assembly Language 4 u Registers -- 32 bits wide –32 general purpose integer registers, known by several names to the assembler  %r0-%r7 also known as %g0-%g7 global registers -- Note, %r0 always contains value 0.  %r8-%r15 also known as %o0-%o7 output registers  %r16-%r23 also known as %l0-%l7 local registers  %r24-%r31 also known as %i0-%i7 input registers t Use the %r0-%r31 names for now. Other names are used in procedure calls. –32 floating point registers %f0-%f31. Each reg. is single precision. Double prec. uses reg. pairs.

CIS36098 SPARC Assembly Language 5 u Assembly language –3-address operations - format different from book op src1, src2, dest !opposite of text E.g., add %r1, %r2, %r3 !%r3  %r1 + %r2 or %r2, 0x0004, %r2 !%r2  %r2 + 0x0004 –Contrast SPARC with MiPs (used in the book) t indirect address notation: @addr vs [addr] t operand order, especially the destination register t register notation: R2 vs. %r2 t branches

CIS36099 SPARC Assembly Language 6 –2-address operations: load and store ld [addr], %r2 ! %r2  M[addr] st %r2, [addr] ! M[addr]  %r2  Often use set to put an address (a label, a symbolic constant) into a register, followed by ld to load the data itself. set x, %r1 !put addr x into %r1 ld [%r1],%r2 !use addr in %r1 to load %r2 –Immediate values: instruction itself contains some data to be used in execution.

CIS360100 SPARC Assembly Language 7 –Immediate values (continued) E.g., add %rs, siconst 13, %rd !%rd  %rs+const t Constant is coded into instruction itself, therefore available after fetching the instruction (no extra trip to memory for an operand). t On SPARC, no special notation for differentiating constants from addresses because no ambiguity in a load/store architecture. t Immediate value coded in 13 bit sign-extended value. Range is, then, -2 12 …2 12 -1 or -4096 to 4095. t Immediate values can be specified in decimal, hexadecimal, or octal. E.g., add %r2, 0x1A, %r2 ! %r2  %r2 + 26

CIS360101 SPARC Assembly Language 8 –Synthetic Instructions: assembler translates one “instruction” into several machine instructions.  set : used to load a 32-bit signed integer constant into a register. Has 2 operands - 32 bit value and register number. How does that fit into a 32 bit instruction? E.g., set iconst 32, %rd set -10, %r3 set x, %r4 set ’=’, %r8  clr %rd : used to set all bits in a register to 0. How?  mov %rs, %rd : copies a register.  neg %rs, %rd : copies the negation of a register.

CIS360102 SPARC Assembly Language 9 –Operand sizes t double word = 8 bytes, word = 4 bytes, half word = 2 bytes, byte = 8 bits. Recall memory alignment issues. set x, %r2 !Put addr x in %r2 ld [%r2], %r1 !load word ldsb [%r2], %r1 !load byte, sign extended ldub [%r2], %r1 !load byte, extend with 0’s st %r1, [%r2] !store word, addr is mult of 4 stb %r1, [%r2] !store byte, any address sth %r1, [%r2] !store half word, address is even – Characters use 8 bits t ldub to load a character t stb to store a character

CIS360103 SPARC Assembly Language 10 –Traps : provides initial help with I/O, also used in operating systems programming.  ta 0 : terminate program  ta 1 : output ASCII character from %r8  ta 2 input ASCII character into %r8  ta 4 : output integer from %r8 in unsigned hexadecimal  ta 5 : input integer into %r8, can be decimal, octal, or hex E.g., set ’=’, %r8 !put ’=’ in %r8 ta 1 !output the ’=’ ta 5 !read in value into %r8 mov %r8, %r1 !copy %r8 into %r1 set 0x0a, %r8 !load a newline into %r8 ta 1 !output the newline

CIS360104 SPARC Assembly Language 11 –More assembler directives (.asciz and.ascii): t Each of the following two directives is equivalent: –msg01:.asciz "a phrase" –msg01:.byte 'a', ' ', 'p', 'h', 'r'.byte 'a', 's', 'e', 0 t Note that.asciz generates one byte for each character between the quote (") marks in the operand, plus a null byte at the end. t The.ascii directive does not generate that extra byte. Each of the following three directives is equivalent: –digits:.ascii "0123456789" –digits:.byte '0', '1', '2', '3', '4', '5'.byte '6', '7', '8', '9' –digits:.byte 0x30, 0x31, 0x32, 0x33, 0x34.byte 0x35, 0x36, 0x37, 0x38, 0x39

CIS360105 SPARC Assembly Language 12 –Quick review of instructions so far:  ld [addr], %rd! %rd  M[addr]  st %rd, [addr]! M[addr]  %r2 t op %rs1, %rs2, %rd! op is ALU op  op %rs, siconst 13, %rd! %rd  %rs op const  set siconst 32, %rd! %rd  const t ta #! trap signal –Have actually seen many more variants, e.g., ldub, ldsb, sth, clr, mov, neg, add, sub, smul, sdiv, umul, udiv, etc. Can evaluate just about any simple arithmetic expression.

CIS360106 Review: Sparc Loads, Stores.data x:.word 0xa1b2c3d4.skip 12.text set x, %r2 ld [%r2], %r3 ldsb [%r2], %r4 ldub [%r2], %r5 st %r3, [%r2+4] sth %r3, [%r2+8] stb %r3, [%r2+12] ta 0 After this runs, what values are in %r2-5, and memory locations starting at byte address x?

CIS360107 Flow of Control 1 u In addition to sequential execution, need ability to repeatedly and conditionally execute program fragments. –High level language has: while, for, do, repeat, case, if-then-else, etc. –Assembler has if, goto. –Compare: high level vs. pseudo-assembler, implementation of f=n! f = 1 i = 2 loop: if (i > n) goto done f = f * i i = i + 1 goto loop done:... f = 1; i = 2; while (i <= n) { f = f * i; i = i + 1; }

CIS360108 Flow of Control 2 –Branch -- put a new address in the program counter. Next instruction comes from the new address, effectively, a “goto”. –Unconditional branch  (book) BRANCH addr ! PC  addr  (SPARC) ba addr ! PC  addr –Conditional branch  (book) BRcc R1, R2, target “if R1 cc R2 then PC  target” and cc is comparison operation (e.g., LT is , GE is , etc.)

CIS360109 Flow of Control 3 –Evaluating conditional branches t Evaluate condition  If condition is true, then PC  target, else PC  PC+1 –Consider changes to the fetch-execute cycle given earlier for accumulator machine. What needs to change?

CIS360110 Flow of Control 4 t Other conditions (from text, very similar to MIPS)  Can implement high level control structures now. Back to the factorial example using the book’s assembly language: LOADR1,#1; R1 = f = 1 LOADR2,#2; R2 = i = 2 LOADR3, n; R3 = n loop:BRGTR2,R3,done; branch if i > n MPYR1,R1,R2; f = f * i ADDR2,R2,#1; i = i + 1 BRANCHloop; goto loop done:STOREf,R1; f = n!

CIS360111 Flow of Control 5 –Condition Codes t Book’s assembly language has 3-address branches. SPARC uses 1-address branches. Must use condition codes. t Non-MIPS machines use condition codes to evaluate branches. Condition Code Register (CCR) holds these bits. SPARC has 4-bit CCR.  N: Negative, Z: Zero, V: Overflow, C: Carry. All are shown in a trace, or in the reg command under ISEM.  Condition codes are not set by normal ALU instruction. Must use special instruction ending with cc, e.g., addcc.

CIS360112 Flow of Control 6.text start: set 1, %r2 set 0xFFFFFFFE, %r1! –2 in 32-bit 2’s comp cc_set: subcc %r1, %r2, %r3! r3<= -2-1 end: ta 0 ISEM> reg ----0--- ----1--- ----2--- ----3--- ----4--- ----5--- ----6--- ----7--- G 00000000 fffffffe 00000001 00000000 00000000 00000000 00000000 00000000 O 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 L 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 I 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 PC: 08:00000028 nPC: 0000002c PSR: 0000003e N:0 Z:0 V:0 C:0 cc_set : subcc %g1, %g2, %g3 ISEM> trace ----0--- ----1--- ----2--- ----3--- ----4--- ----5--- ----6--- ----7--- G 00000000 fffffffe 00000001 fffffffd 00000000 00000000 00000000 00000000 O 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 L 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 I 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 PC: 08:0000002c nPC: 00000030 PSR: 00b0003e N:1 Z:0 V:0 C:0

CIS360113 Flow of Control 7 –Setting the condition codes t Regular ALU operations don’t set condition codes.  Use addcc, subcc, smulcc, sdivcc, etc., to set condition codes.  E.g., Suppose %r1 contains -4 and %r2 contains 5. addcc %r1, %r2, %r3 subcc %r1, %r2, %r3 subcc %r2, %r1, %r3 subcc %r1, %r1, %r3

CIS360114 ALU Hardware 1 u How does a computer add? –Design a circuit that adds three single digit binary numbers. Results in a sum, and a carry out.    xy c out c in Sum FA xy c out c in Sum

CIS360115 ALU Hardware 2 u Now cascade the full adder hardware u How are CCR bits set? –C-bit = C out –V-bit = C out  C n-1 –Z-bit =  (rz 0  rz 1  rz 2 ...  rz n-1 ) –N-bit = rz n-1 FA 0 register xregister y register z FA c out FA

CIS360116 Flow of Control 8 –Branches use logic to evaluate CCR (SPARC) OperationAssembler SyntaxBranch Condition Branch always batarget 1 (always) Branch never bntarget 0 (never) Branch not equal bnetarget ZZ Branch equal betarget Z Branch greater bgtarget  (Z  (N  V)) Branch less or equal bletarget (Z  (N  V)) Branch greater or equal bgetarget  (N  V) Branch less bltarget N  V Branch greater, unsigned bgutarget  (C  Z) Branch less or equal, unsigned bleutarget C  Z Branch carry clear bcctarget CC Branch carry set bcstarget C Branch positive bpostarget NN Branch negative bnegtarget N Branch overflow clear bvctarget VV Branch overflow set bvstarget V

CIS360117 Flow of Control 9 –Setting Condition Codes (ctd).  Synthetic instruction cmp %rs1, %rs2 –Sets CCR, but doesn't modify any registers. –Implemented as subcc %rs1, %rs2, %g0 t Back to the factorial example (SPARC) set 1, %r1! %r1 = f = 1 set 2, %r2! %r2 = i = 2 set n, %r3! Get loc of n ld [%r3], %r3! Put n in %r3 loop:cmp %r2, %r3! Set CCR (i?n) bg done! i > n done nop! Branch delay umul %r1, %r2, %r1! f = f * i add %r2, 1, %r2! i = i + 1 ba loop! Goto loop nop! Branch delay done:set f, %r3! Get loc of f st %r1, [%r3]! f = n!

CIS360118 Flow of Control 10 –Branch delay slots: unique to RISC architecture t Non-technical explanation: processor is running so fast, it can’t make a turn. –Instruction following branch is always executed. t Technical explanation: pipelining doesn't permit a decision about a branch taken until after the next instruction enters the pipeline. t Compilers take advantage of branch delay slots by putting a useful instruction there if possible.  For our purposes, use the nop (no operation) instruction to fill branch delay slots. Beware! Forgetting the nop will be a large source of errors in your programs!

CIS360119 High Level Control Structures 1 u Converting high level control structures –You get to be the “compiler”. t Some compilers convert the source language (C, Pascal, Modula 2, etc.) into assembly language and then assemble the result to an object file. GNU C, C++ do this to GAS (Gnu Assembler). –if-then-else, while-do, repeat-until are all possible to create in a structured way in assembly language.

CIS360120 High Level Control Structures 2 u General guidelines –Break down into independent logical units –Convert to if/goto pseudo-code. –Mechanical, step-by-step, non-creative process f=1 i=2 loop: if (i>n) goto done f = f*i i = i+1 goto loop done:... f = 1; for (i=2; i<=n; i++) f = f * i;

CIS360121 High Level Control Structures 3 t if-then-else if (a<b) c = d + 1; else c = 7; t if/goto if (a >= b) goto else c = d + 1 goto end else: c = 7 end: init: set a, %r2 ! get &a into r2 ld [%r2], %r2 ! get a into r2 set b, %r3 ! get &b into r3 ld [%r3], %r3 ! get b into r3 if: cmp %r2, %r3 ! a ?? b (want >=) bge else ! a >= b, do then nop set d, %r5 ! get &d into r5 ld [%r5], %r5 ! get d into r5 add %r5, 1, %r4 ! r4 <- d+1 ba end nop else: set 7, %r4 ! get 7 into r4 end: set c, %r5 ! get &c into r5 st %r4, [%r5] ! c <- r4

CIS360122 High Level Control Structures 4 u while loops: while (a<b) a = a+1; c = d; u if/goto: whle:if (a>=b) goto done body:a = a+1 goto whle done:c = d init: set a, %r4 ! get &a into r4 ld [%r4], %r2 ! get a into r2 set b, %r3 ! get &b into r3 ld [%r3], %r3 ! get b into r3 whle: cmp %r2, %r3 ! a ?? b (want >=) bge done ! a >= b skip body nop body: add %r2, 1, %r2 ! r2 = a + 1 st %r2, [%r4] ! a = a + 1 ba whle ! repeat loop body nop done: set c, %r5 ! get &c into r5...

CIS360123 High Level Control Structures 5 t repeat-until loops: repeat … until (a>b) t if/goto: repeat: … if (a<=b) goto repeat nop

CIS360124 High Level Control Structures 6  Complex condition if((a =c)) … if((a =c)) … u These can be combined and used in if/else or while loops.

CIS360125 Flow of Control 11 –Optimizing code: change order of instructions, combine instructions, take advantage of branch delay slots.  Factorial example again. ( for i:=n downto 1 do… ) t Reduced 7 instructions in loop to just 4. t (You gain no advantage if you optimize code in your labs.) set 1, %r1 ! %r1=f=1 set n, %r2! Get loc of n ld [%r2], %r2! Put n in %r2 loop:umul %r1, %r2, %r1! f=f*n subcc %r2, 1, %r2! Decrement n bg loop! Repeat nop! Branch delay set f, %r3! Get loc of f st %r1, [%r3]! f=n!

CIS360126 Synthetic Instructions u Remember Lab0?.data x:.word 0x42 y:.word 0x20 z:.word 0.text start: set x, %r2 ld [%r2], %r2 set y,%r3 ld [%r3], %r3 and so on… Suppose you gave this command to ISEM (after loading): ISEM> dump start start 05 00 00 08 84 10 a0 60 c4 00 80 00 07 00 00 08 Could you find the set instruction?

CIS360127 Instruction Encodings 1 u First, Instruction Encoding is how instructions are assembled –All instructions must fit into 32 bits.  Register-register: op=10, i=0  Register-immediate: op=10, i=1  Floating point: op=10, i=0

CIS360128 Instruction Encodings 2  Call instructions: op=01  Branch instructions: op=00, op2=010  SETHI instructions: op=00, op2=100  Ex.: add %r2, %r3, %r4 in hexadecimal: 88008003 a

CIS360129 Understanding SET Synthetic Usually used to put the value of an address in memory into a register. For example, set 0x4004, %r3 Can do neither ‘add %r0, 0x4004, %r3’ nor ‘or %r0, 0x4004, %r3’. Why not? SET is a synthetic instruction which may be implemented in two steps. #2 #1 Machine language encoding for 'set 0x4004, %r3'

CIS360130 Decoding an Instruction 05 00 00 08 16 0000 0101 0000 0000 0000 0000 0000 1000 2 Instruction Group (bits 30:31) = 00 Destination Register (bits 25:29) = 00010 Op Code (bits 22:24) = 100 Constant (bits 0:21) = 0000000000000000001000 Meaning: sethi 0x8, %r2 %r2 <-- 00000000000000000010000000000000 (0x2000)

CIS360131 More Decoding 07 0000 08 86 10 E0 64

CIS360132 SET Synthetic Instruction u set iconst, rd sethi %hi(iconst), rd or rd, %lo(iconst), rd --or-- sethi %hi(iconst), rd --or-- or %g0, iconst, rd

CIS360133 Bitwise Operations 1 u Bit Manipulation Instructions –Bitwise logical operations t and %rs1, %rs2, %rd 10010011… (32 bits) 01111001… t or %rs1, %rs2, %rd 10010011… (32 bits) 01111001… t xor %rs1, %rs2, %rd 10010011… (32 bits) 01111001…

CIS360134 Bitwise Operations 2 t andn %rs1, %rs2, %rd 10010011… (32 bits) 01111001…  orn %rs1, %rs2, %rd 10010011… (32 bits) 01111001… t not %rs, %rd 10010011… (32 bits)  Recall the cc operations, so andcc, orcc, etc. are available. (However, there is no notcc ; use xnorcc.)

CIS360135 Bitwise Operations 3  For what kinds of things are these bit level operations used? Recall the synthetic operation clr, and mov. clr %r2  or %r0, %r0, %r2 mov %r2 %r3  or %r0, %r2, %r3 t Masking operations: Want to select a bit or group of bits from a set of 32. E.g., convert lower (or upper) to upper case: ‘ a ’ in binary is 01100001 ‘ A ’ in binary is 01000001 All we need to do is “turn off” the bit in position 5. 0xDF in binary is 11011111 and %r1, 0xDF, %r1 will turn off that bit! t What if we subtract 32 from %r1? t What about converting upper to lower case?

CIS360136 Bitwise Operations 4 –Bitwise shifting operations  Shift logical left: sll %rs1, %rs2, %rd %rs1 : data to be shifted %rs2 : shift count %rd : destination register E.g., set 0xABCD1234, %r2 sll %r2, 3, %r3 %r2: 1010 1011 1100 1101 0001 0010 0011 0100 %r3: 0101 1110 0110 1000 1001 0001 1010 0000 t sll is equivalent to multiplying by a power of 2 (barring overflow). (In the decimal system, what’s a shortcut for multiplying by a power of ten?)

CIS360137 Bitwise Operations 5  Shift Logical Right: srl %rs1, %rs2, %rd –Shifts right instead of left, inserting zeros.  Arithmetic shifts: propagate the sign bit when shifting right, e.g., sra. (Left shift doesn't change.) –Equivalent to dividing by a power of 2. t Rotating shifts: Bits that would have gone into the bit bucket are shifted in instead. (E.g., rr, rl) –Rotate not implemented in SPARC

CIS360138 More SPARC Assembly Language Assembler directives t Are not encoded as machine instructions  Memory alignment:.align 4 –Used when mixing allocations of bytes, words, halfwords, etc. and need word boundary alignment  Reserve bytes of space:.skip 20 –Useful for allocating large amounts of space (e.g., arrays)  Create a symbolic constant:.set mask, 0x0f –Can now use the word “mask” anywhere we could use the constant 0x0f previously All this is leading to additional addressing modes, which help us work with pointers, arrays, and records in assembly language.

CIS360139 Addressing Modes 1 u Addressing Modes –How do we specify operand values? t In a register, location is encoded in the instruction. t As a constant, immediate value is in the instruction. t In memory, operand is somewhere in memory, location may only be known at runtime. –Memory operands: t Effective address: actual location of operand in memory. This may be calculated implicitly (e.g., by a displacement in the instruction) or may be calculated by the programmer in code.

CIS360140 Addressing Modes 2 –Summary of addressing modes:

CIS360141 Addressing Modes 3 –Memory Direct addressing t Entire address is in the instruction (not in SPARC). E.g., accumulator machine: each instruction had an opcode and a hard address in memory. –Can’t be done on SPARC because an address is 32 bits, which is the length of an instruction. No room for opcodes, etc. Can be done in CISC because multi-word instructions are permitted. –Memory Indirect addressing t Pointer to operand is in memory. Instruction specifies location of pointer. Requires three memory fetches (one each for instruction, pointer, and data). Not in RISC machines because instruction is too slow; such an instruction would cause its own register interlock!

CIS360142 Addressing Modes 4 –Register Indirect addressing t Register has address of operand (a pointer). Instruction specifies register number, effective address is contents of register. Ex.:.data n:.word 5; initialize [n] to 5.text set n, %r1; %r1 has pointer to [n] ld [%r1], %r3; fetch [n] into %r3

CIS360143 Addressing Modes 5 t Ex.: sum up array of integers:.data n:.word 5! Size of array a:.word 4,2,5,8,3! 5 word array sum:.word 0! Sum of elements b:.skip 5*4! another 5 word array.text clr %r2! r2 will hold sum set n, %r3! r3 points to [n] ld [%r3], %r3! r3 gets array size set a, %r4! r4 points to array loop:ld [%r4], %r5! Load element of a into r5 add %r5, %r2, %r2! sum = sum + element add %r4, 4, %r4! Incr ptr by word size subcc %r3, 1, %r3! Decrement counter bg loop! Loop until count = 0 nop! Branch delay slot set sum, %r1! r1 points to sum st %r2, [%r1]! Store sum ta 0! done 05a 4a+4 3a+8 2a+12 1a+16 r2 r3 r4 r5 Pre-loop loop loop+1 loop+2 loop+3 5 n a a+4 a+8 a+12 a+16 sum 4 2 5 8 3

CIS360144 Addressing Modes 6  C-style example of pointer data type charx;// object of type character char *ptr;// pointer to character type ptr = &x;// ptr has address of x (points to x) *ptr = ‘a’;// store ‘a’ at address in ptr  Assembly language equivalent.data x:.byte 0 ! reserve character space.align 4 ! align to word boundary ptr:.word 0 ! pointer variable.text set x, %r1! get address x into %r1 set ptr, %r2! get address ptr into %r2 st %r1, [%r2]! make [ptr] point to [x] set ’a’, %r3! put character ‘a’ into r3 stb %r3, [%r1]! store ‘a’ at address x x ptr ‘a’ Addr of x X: ptr: r1 r2 r3

CIS360145 Addressing Modes 7 –Register Indexed addressing t Suitable for accessing successive elements of the same type in a data structure.  Ex.: Swap elements A[i] and A[k] in array t Effective address calculations! A A+4 A+8 A+12 0010010 A 1001000 r2 r3 r4 r7 r8 after sll <-

CIS360146 Addressing Modes 8 t Simulating Register Indirect addressing on SPARC –SPARC doesn't truly have register indirect addressing. We can write st %r2, [%r1] but assembler converts this automatically into st %r2, [%r1+%r0] t Array mapping functions: used by compilers to determine addresses of array elements. Must know upper bound, lower bound, and size of elements of array. –Total storage = (upper - lower + 1)*element_size –Offset for kth element = (k - lower)*element_size –Offset for A[3] = (3-0)*4 = 12 –This is for 1 dimensional arrays only!

CIS360147 Addressing Modes 9 t 1D array mapping functions: Want an array of n elements, each element is 4 bytes in size, array starts at address arr. –Total storage is 4n bytes –First element is at arr+0 –Last element is at arr+4(n-1) –k th (k can range from 0…n-1) element is at arr+4k. Array uses zero-based indexing.

CIS360148 Addressing Modes 10 t 2D array mapping functions: must linearize the 2D concept; e.g., map the 2D structure into 1D memory. –Convert into 1D array in memory

CIS360149 Addressing Modes 11 t 2 ways to convert to 1D –Row major order (Pascal, C, Modula-2) stores first by rows, then by columns. E.g., –Column major order (FORTRAN) stores first by columns then by rows. E.g., –Row major 2D array mapping function: Given an array starting at address arr that is x rows by y columns, each element is m bytes in size, and indices start at zero, then element (i, j) may be found at location: arr + (y  i + j)  m

CIS360150 Addressing Modes 12 t 3D array mapping function: natural extension of 2D function. Store by row, then column, then depth. –Array starting at arr with x rows, y columns, depth z, m element size. Element (i, j, k) is found at location: arr + (z  y  i + j) + k)  m 1,0,0 +0 +1 +2+4+6+8 +3+5+7+9 +10+12+14+16+18

CIS360151 Addressing Modes 13 CALCULATE: total storage offset for A(i,j,k) address for A(i,j,k) 1D2D3D element size (#bytes)421 # rows (x)733 # cols (y)155 # depth (z)112 starting addr (0)4812 i=110 j=011 k=001

CIS360152 Addressing Modes 14 ! Example that adds 1 to every element of columns 1 and 2, not 0, of a 5 by 3 array.data.set rows, 5 ! define symbolic constants.set cols, 3 arr:.skip rows * cols * 4! allocate space (.skip 60 same).text... setarr, %r3! get address of array clr%r1! %r1 is i (row) loop1:cmp%r1, rows! done if i >= rows bgedone nop clr%r2! %r2 is j (col), inc%r2! start at one (skip col zero) loop2: cmp%r2, cols! if at last column, done with row bgeinc1 nop smul%r1, cols, %r4! # elements to skip for current row add%r4, %r2, %r4! then which column being accessed smul%r4, 4, %r4 ! change from element to byte offset ld[%r3+%r4], %r5! get arr[i][j] add%r5, 1, %r5 ! increment value st%r5, [%r3+%r4]! store it back to arr[i][j] inc2:add%r2, 1, %r2 ! next column baloop2! continue inner loop over columns nop inc1:add%r1, 1, %r1 ! next row baloop1! continue outer loop over rows nop done:...

CIS360153 Addressing Modes 15 –Displacement Addressing t Suitable for accessing the individual fields of record data structures. Each field can be of a different type.  Use.set directive to establish offsets to fields within records. Then use displacement addressing to access those fields.

CIS360154 Addressing Modes 16 t Ex.: Add 1 to the age field in a person record t Problem: alignment in memory. May have to waste some space in the person record in order to have the integer fields align on a word boundary.

CIS360155 Addressing Modes 17 –Auto-increment and Auto-decrement addressing t SPARC does not support these modes. They may be simulated using register indirect addressing followed by an add or subtract of the size of the element on that register. t Useful for traversing arrays forward (auto-increment) and backward (auto-decrement). Also useful for stacks and queues of data elements.

CIS360156 Subroutines 1 –Subroutines and subroutine linkage t Subroutines: programming mechanism to facilitate repeated computations and modularization. –Use of subroutines t Basis for structured and disciplined programming t Compact code (no need to write monolithic loops) t Relatively easy to debug (no cut-and-paste errors) t Requires little hardware support, mostly protocols and conventions to handle parameters.

CIS360157 Subroutines 2 –Terminology t Caller: the code (which could be a subroutine itself) which invokes the subroutine of interest t Callee: the subroutine being invoked by the caller t Function: subroutine that returns one or more values back to the caller and exactly one of these values is distinguished as the return value t Return value: the distinguished value returned by a function

CIS360158 Subroutines 3 –Terminology (continued) t Procedure: a subroutine that may return values to the caller (through the subroutine’s parameter(s)), but none of these values is distinguished as the return value t Return address: address of the subroutine call instruction t Parameters: information passed to/from a subroutine (a.k.a. arguments) t Subroutine linkage: a protocol for passing parameters between the caller and the callee

CIS360159 Subroutines 4 –Subroutine linkage t Calling a subroutine –Assembly language syntax for calling a subroutine call label nop –Must change the program counter (as in a branch instruction) however, we must also keep track of where to resume execution after the subroutine finishes. Call instruction handles this atomically (i.e., without interruption) by: %r15  PC nPC  label t Returning from a subroutine –Assembly language syntax for returning from a subroutine retl nop

CIS360160 Subroutines 5 t Returning from a subroutine (continued) –Again, must change the program counter to return to an instruction after the one that called the subroutine. The address of the instruction that called it was saved in %r15, and we must skip over the branch delay slot as well. So, this is accomplished by: nPC  %r15+8 t Parameter passing: 2 approaches –Register based linkage: pass parameters solely through registers. Has the advantage of speed, but can only pass a few parameters, and it won’t support nested subroutine calls. Such a subroutine is called a leaf subroutine. –Stack based linkage: pass parameters through the run-time stack. Not as fast, but can pass more parameters and have nested subroutine calls (including recursion).

CIS360161 Register-based Linkage 1 –Register based linkage : t Startup Sequence: load parameters and return address into registers, branch to subroutine. t Prologue: if non-leaf procedure then save return address to memory, save registers used by callee. t Epilogue: place return parameters into registers, restore registers saved in prologue, restore saved return address, return. t Cleanup Sequence: work with returned values

CIS360162 Register-based Linkage 2 –Example: Print subroutine..text main:set1, %r1! Initialize r1 and r2 set3, %r2 mov%r1, %r8! Print %r1 callprint nop mov%r2, %r8! Print %r2 callprint nop add%r1, %r2, %r8! Do our calculation callprint! Print the result (expect ‘4’) nop ta0 print:set‘0’, %r1! Ascii value of zero add%r8, %r1, %r2! Treat r8 as parameter mov%r2, %r8! Move into output register ta1! Output character mov‘\n’, %r8 ta1! Output end of line (newline) retl! Return nop t What’s wrong with the above code?

CIS360163 Register-based Linkage 3 –Which registers can subroutines change? t Convention for optimized leaf procedures: t Any other registers the subroutine touches must be saved to memory somewhere, and restored before returning to the caller. t Problem: how can a subroutine call another subroutine? How can a subroutine call itself?

CIS360164 Register-based Linkage 4 –Example: procedure to print linked list of ints. nop

CIS360165 Parameter Passing 1 –Parameter passing review: t Pass by value: parameters to subroutine are copies upon which the subroutine acts. t Pass by reference: parameters to subroutine are addresses of values upon which the subroutine acts. Callee is responsible for saving each result to memory at the location referred to by the appropriate parameter. t Hybrid: some parameters passed by value, and some by reference. Callee is responsible for saving results for reference parameters.

CIS360166 Parameter Passing 2 –Parameter passing notes: t Array or record parameters typically are passed by reference (efficiency reasons). Primitive data types may be passed either way. t Conventions among languages allows any language to call functions in any other language: –Pascal: VAR parameters are passed by reference; all others are passed by value. –C: all parameters are passed by value. Must explicitly pass a pointer if you want a reference parameter. –C++: like Pascal, can pass by value or by reference. –FORTRAN: all things passed by reference (even constants). –ADA: pass by value/result.

CIS360167 Parameter Passing 3.text ! pp. 72-73 of Lab Manual ! pr_str – print a null terminated string ! Parameters: %r8 – pointer to string (initially) ! ! Temporaries: %r8 – the character to be printed ! %r9 – pointer to string ! pr_str: mov %r8, %r9 ! we need %r8 for the “ta 1” below pr_lp: ldub [%r9], %r8 ! load character cmp %r8, 0 ! check for null be pr_dn nop ta 1 ! print character ba pr_lp inc %r9 ! increment the pointer ! (in a branch delay slot!) pr_dn: retl nop

CIS360168 Parameter Passing 4 t Summary from text (p. 220) –Pass by value: For small “in” parameters. Subroutines cannot alter the originals whose copies are passed as parameters. –Pass by value/result: For small “in/out” parameters. Caller’s cleanup sequence stores values of any “in/out” parameters. –Pass by reference: for “in/out” parameters of all sizes, and large “in” parameters. “Out” values are provided by changing memory at those addresses. (Note: pass by reference is passing an address by value).

CIS360169 Parameter Passing 5 –Write Sparc code for the caller and callee for the following subroutine using register based parameter passing ! global_function Integer Subchr (A, B, C) ! Substitutes character C for all B in string [A], ! and returns count of changes. ! ! // In comments, "[A+index]" is denoted by "ch". ! index = 0 ! count = 0 ! LOOP: if [A+index]=0 go to END // while (ch != 0) { ! if [A+index]  B go to INC // if (ch == B) { ! [A+index]=C // ch = C; ! count=count+1 // count++; } ! INC: index=index+1 // index++; ! go to LOOP // } ! END:.data! data section C_s:.byte ’I’ ! parameter C B_s:.byte ’i’ ! parameter B A_s:.asciz "i will tip"! parameter A.align 4 R_s:.word 0! for storing result count Assume

CIS360170 Stack-based Linkage 1 u Stack based linkage –Advantages t Allows a larger number of parameters to be passed. t Permits records and arrays to be passed by value. t Saving of registers by callee is “built-in”. t A way for callee to reserve memory for other uses is “built-in”, too. –Disadvantages t Slower than register based t More complex protocol –Why a stack? t Subroutine calls and returns happen in a last-in first-out order (LIFO). Also known as a runtime stack, parameter stack, or subroutine stack.

CIS360171 Stack-based Linkage 2 t Items “saved” on the stack in one activation record –Parameters to the subroutine –Registers used in the subroutine –Local memory variables used in subroutine –Return value and return address  Say A() calls B(), B() calls C(), and C() calls A()

CIS360172 Stack-based Linkage 3 –Stack based linkage parameter passing convention t Startup sequence: –Push parameters –Push space for return value t Prologue –Push registers that are changed (including return address) –Allocate space for local variables t Epilogue –Restore general purpose registers –Free local variable space –Use return address to return t Cleanup Sequence –Pop and save return values –Pop parameters

CIS360173 Stack-based Linkage 4 –Stack based parameter passing example:  Register %r14  %sp  stack pointer –Invariant: Always indicates the top of the stack (it has the address in memory of the last item on stack, usually a word). –Moved when items are “pushed” onto the stack. –Due to interruptions (system interrupts (I/O) and exceptions), values stored above %sp (at addresses less than %sp) can change at any time! Hence, any access above %sp is unsafe!  Register %r30  %fp  frame pointer –Indicates the previous stack pointer. Activation record is from (some subroutine-specific number of words before) the %fp to the %sp. –Invariant: %fp is constant within a subroutine (after prologue).

CIS360174 Stack-based Linkage 5 –Stack based parameter passing example: t Want to implement the following subroutine: ! global_function Integer Subchr (A, B, C) ! Substitutes character C for all B in string A, ! and returns count of changes. ! ! // In comments, "*(A+index)" is denoted by "ch". ! index = 0 ! count = 0 ! LOOP: if *(A+index)=0 go to END // while (ch != 0) { ! if *(A+index)  B go to INC // if (ch == B) { ! *(A+index)=C // ch = C; ! count=count+1 // count++; } ! INC: index=index+1 // index++; ! go to LOOP // } ! END:.data! data section C_s:.byte ’I’ ! parameter C B_s:.byte ’i’ ! parameter B A_s:.asciz "i will tip"! parameter A.align 4 R_s:.word 0! for storing result count

CIS360175 Stack-based Linkage 6.data! data section C_s:.word ’I’ ! parameter C B_s:.word ’i’ ! parameter B A_s:.asciz "i will tip"! parameter A.align 4 ! align to word address stack:.skip 250*4! allocate 250 word stack bstak: ! point to bottom of stack R_s:.word 0! reserve for count.text ! Program’s one-time initialization start: set bstak, %sp! set initial stack ptr mov %sp, %fp! set initial frame ptr ! STARTUP SEQUENCE to call subchr() sub %sp, 16, %sp! move stack ptr set A_s, %r1! A is passed by reference st %r1, [%sp+4]! push address on stack set B_s, %r1! B is passed by value ld [%r1], %r1! get value of B st %r1, [%sp+8]! push parameter B on stack set C_s, %r1! C is passed by value ld [%r1], %r1! get value of C st %r1, [%sp+12]! push parameter C on stack ! SUBROUTINE CALL call subchr! make subroutine call nop! branch delay slot ! CLEANUP SEQUENCE ld [%sp], %r1! pop return value off stack add %sp, 16, %sp! pop stack set R_s, %r2! get address of R st %r1, [%r2]! store R...! the rest of the program Return value b stack: %sp -> %fp -> addr (a) c

CIS360176 Stack-based Linkage 7 ! SUBROUTINE PROLOGUE subchr: sub %sp, 32, %sp! open 8 words on stack st %fp, [%sp+28]! Save old frame pointer add %sp, 32, %fp! old sp is new fp st %r15, [%fp-8]! save return address st %r8, [%fp-12] ! Save gen. Register … ! Save r9-r13, omitted ! SUBROUTINE BODY ld_reg: ld [%fp+4], %r8! “pop” (load) addr of A ld [%fp+8], %r9! “pop” (load) value of B ld [%fp+12], %r10! “pop” (load) value of C clr %r12! count clr %r13! index loop: ldub [%r8+%r13], %r11! load a string chr cmp %r11, 0x0! is chr=null? be done! then go to done cmp %r11, %r9! is chr<>B? (branch delay) bne inc! then go to inc nop! branch delay slot stb %r10, [%r8+%r13] ! change chr to C add %r12, 1, %r12! increment count inc: add %r13, 1, %r13! increment index ba loop! do next chr nop! branch delay slot done: st %r12, [%fp+0]! “push” (store) count on stack ! EPILOGUE … ! Restore r9-r13, omitted ld [%fp-12], %r8 ! Restore r8 ld [%fp-8], %r15! get saved return address ld [%fp-4], %fp! Get old value of frame ptr add %sp, 32, %sp! Restore stack pointer retl! return to caller nop! branch delay slot c b addr (a) %sp -> %fp -> return addr old frame ptr Return value... %r9 %r8

CIS360177 Stack-based Linkage 8 u General Guidelines –Keep Startups, Cleanups, Prologues, and Epilogues standard (but not necessarily identical); easy to cut, paste, and modify. –Caller: leave space for return value on the TOP of the stack. –Callee: always save and restore locally used registers (except %r1). –Pass data structures and arrays by reference, all others by value (efficiency).

CIS360178 Traps and Exceptions 1 u Traps and Exceptions –Other side of low level programming -- the interface between applications and peripherals –OS provides access and protocols

CIS360179 Traps and Exceptions 2 –BIOS: Basic Input/Output System t Subroutines that control I/O t No need for you to write them as application programmer t OS interfaces application with BIOS through traps (extended operations (XOPs))

CIS360180 Traps and Exceptions 3 –Where are OS traps kept? Two approaches: t Transient monitor: traps kept in a library that is copied into the application at link-time t Resident monitor: always keep OS in main memory; applications share the trap routines. t OS routines monitor devices. Frequently used routines kept resident; others loaded as needed.

CIS360181 Traps and Exceptions 4 –(Assuming a res. monitor) How to find I/O routines?  Store routines in memory, and make a call to a hard address. E.g., call 256 –When new OS is released, need to recompile all application programs to use different addresses. t Use a dispatcher –Dispatcher is a subroutine that takes a parameter (the trap number). Dispatcher knows where all routines actually are in memory, and makes the branch for you. Dispatcher subroutine must always exist in the same location. 2

CIS360182 Traps and Exceptions 5 t Use vectored linking –Branch table exists at a well known location. The address of each trap subroutine is stored in the table, indexed by the trap number. –On RISC, usually about 4 words reserved in the table. If the trap routine is larger than 4 words, can branch to the actual routine.

CIS360183 Traps and Exceptions 6 –Levels of privilege t Supervisor mode - can access every resource t User mode - limited access to resources t OS routines operate in supervisor mode, access is determined by bit in PSW (processor status word).  XOP (book’s notation) can always be executed, sets privilege to supervisor mode ( ta )  RTX (book’s notation) can only be executed by the OS, and returns privilege to user mode ( rett ) –Exceptions t Caused by invalid use of resource. E.g., divide by zero, invalid address, illegal operation, protection violation, etc.

CIS360184 Traps and Exceptions 7 t Control transferred automatically to exception handler routine. Similar to trap or XOP transfer. t Exceptions vs. XOPs –XOPs explicit in code, exceptions are implicit –XOPs service request and return to application; exceptions print message and abort (unless masked). –Trap example: non-blocking read ta 3 t If there is nothing in the keyboard buffer, return with a message that nothing is there. Otherwise, put the character into register 8.

CIS360185 Traps and Exceptions 8 t Status of the keyboard is kept in a memory location, as is the (one-character) keyboard buffer. Memory mapped devices. t On SPARC, trap table has 256 entries. 0-127 are reserved for exceptions and external interrupts. 128-255 are used for XOPs. Trap table begins at address 0x0000. Each entry is 4 instructions (16 bytes) long.

CIS360186 Traps and Exceptions 9 t Trap execution: ta 3 –Calculate trap address: 3 * 16 + 0x0800 = 16 * (3 + 0x080) –Save nPC and PSW to memory SPARC uses register windows Assumes local registers are available –Set privilege level to supervisor mode –Update PC with trap address (and make nPC = PC + 4) (jumps to trap table) –Trap table has instruction ba ta3_handler –rett Restores PC (from saved nPC value) and PSW (resets to user mode) Returns to application program

CIS360187 Programmed I/O 1 u Programmed I/O –Early approach: Isolated I/O t Special instructions to do input and output, using two operands: a register and an I/O address. t CPU puts device address on address bus, and issues an I/O instruction to load from or store to the device.

CIS360188 Programmed I/O 2 Isolated I/O

CIS360189 Memory Mapped I/O t No special instructions. Treat the I/O device like a memory address. Hardware checks to see if the memory address is in the I/O device range, and makes the adjustment. t Use high addresses (not “real” memory) for I/O memory maps. E.g., 0xFFFF0000 through 0xFFFFFFFF. CPU Memory I/O addr bus data bus read/write

CIS360190 Programmed I/O 3 –Advantages of each t Memory mapped: reduced instruction set, reduced redundancy in hardware. t Isolated: don’t have to give up memory address space on machines with little memory

CIS360191 Programmed I/O - UARTs t UARTs –Universal Asynchronous Receiver Transmitter –Asynchronous = not on the same clock. –Handshake coordinates communication between two devices. –A kind of programmed I/O. KeyboardUART 0 1 0 CPU. 0 01101010 serial parallel

CIS360192 UARTs 1 u UART registers –Control: set up at init, speed, parity, etc. –Status: transmit empty, receive ready, etc. –Transmit: output data –Receive: input data –All four needed for bi- directional communications, –Status/control, transmit / receive often combined. Why? Control Reg Status Reg Transmit Reg Receive Reg Transmit Logic Receive Logic Control bus Address bus Data bus

CIS360193 UARTs 2 u Memory mapped UARTs –Both memory and I/O “listen” to the address bus. The appropriate device will act based on the addresses. –Keyboards and Printers require three addresses (when addresses are not combined). –Modems require four. –(why?) UART 1 data UART 1 status UART 1 control UART 2 xmit UART 2 recv UART 2 status UART 2 control UART 3 xmit FFFF 0000 FFFF 0004 FFFF 0008 FFFF 000C FFFF 0010 FFFF 0014 FFFF 0018 FFFF 001C CPU MemoryUART1UART2 Control bus Address bus Data bus and so on

CIS360194 Programmed I/O 4 u Programmed I/O Characteristics: –Used to determine if device is ready (can it be read or written). –Each device has a status register in addition to the data register. –Like previous trap example, must check status before getting data. –Involves polling loops.

CIS360195 Programmed I/O – Polling Ex.: ta 2 handler (blocking keyboard input) u Can’t afford to wait like this. Computer is millions of times faster than a typist. Also, multi-tasking operating systems can’t wait. u Special purpose computers can wait. E.g., microwave oven controllers. u Must have a better way! Interrupts are the answer! Are you ready?... Are you ready now?... How about NOW?... Nope.. Not yet.. Hang on..

CIS360196 Interrupts and DMA transfers 1 u Programmed (polled) I/O used busy waiting. –Advantages: simpler hardware –Disadvantages: wastes time u Interrupts (IRQs on PCs) –I/O device “requests” service from CPU. –CPU can execute program code until interrupted. Solves busy waiting problems. –Interrupt handlers are run (like traps) whenever an interrupt occurs. Current application program is suspended.

CIS360197 Interrupts and DMA transfers 2 u Servicing an interrupt –I/O controller generates interrupt, sets request line “high”. –CPU detects interrupt at beginning of fetch/execute cycle (for interrupts “between” instructions). –CPU saves state of running program, invokes intrpt. handler. –Handler services request; sets the request line “low”. –Control is returned to the application program. Application Program : *Interrupt Detected* : Interrupt Handler Service Request : Clear Interrupt

CIS360198 Interrupts and DMA transfers 3 u Changes to fetch/execute cycle u Problems –Requires additional hardware in Timing & Control. –Queuing of interrupts –Interrupting an interrupt handler (solution: priorities and maskable interrupts) –Interrupts that must be serviced within an instruction –How to find address of interrupt handler Interrupt Pending? Save PC Save PSW PSW=new PSW PC=handler_addr PC -> bus load MAR INC to PC load PC YN

CIS360199 Interrupts and DMA transfers 4 u Example: interrupt driven string output –Want to print a string without busy waiting. –Want to return to the application as fast as possible I’m ready!

CIS360200 Trap handler implementation u Install trap handler into trap table –Buffer is like circular queue –only outputs, at most, one character disp_buf:.skip 256 ! buffers string to print disp_frnt:.byte 0 ! offset to front of queue disp_bck:.byte 0 ! offset to back of queue ta_6_handler: ! Copy str from mem[%r8] to mem[disp_buf+disp_bck] ! Disp_back = (disp_back+len(str)) mod 256 ! If display is ready ! If first char is not null, then output it ! Disp_frnt = (disp_frnt+1) mod 256 rett ! Return from trap Disp_buf: disp_frnt  disp_bck  newest byte Undisplayed byte Oldest byte

CIS360201 Interrupt handler implementation u This too outputs only one character at most, but when display becomes ready again, it generates another interrupt which invokes this routine! display_IRQ_handler: ! Save any registers used ! If disp_frnt != disp_bck (queue is not empty) ! Get char at mem[disp_frnt] ! If char is not null, then output it ! Disp_frnt = (disp_frnt+1) mod 256 ! Restore registers and set the request line “low” rett ! Return from trap u Uses the UART for transmission. I’m ready! CPU Memory

CIS360202 Interrupts and DMA transfers 5 u Problems with interrupt driven I/O t CPU is involved with each interrupt t Each interrupt corresponds to transfer of a single byte t Lots of overhead for large amounts of data (blocks of  512 bytes) MemoryCPU Device Controller Execute 10s or 100s of instructions per byte Transfer one word of data Interrupt Transfer one byte of data

CIS360203 Interrupts and DMA transfers 6 u DMA (Direct Memory Access) t Want I/O without CPU intervention t Want larger than one byte data transfers t Solution: add a new device that can talk to both I/O devices and memory without the CPU; a “specialized” CPU strictly for data transfers. Memory CPU Device Controller DMA Controller

CIS360204 Interrupts and DMA transfers 7 u Steps to a DMA transfer –CPU specifies a memory address, the operation (read/write), byte count, and disk block location to the DMA controller. –DMA controller initiates the I/O, and transfers the data to/from memory directly –DMA controller interrupts the CPU when the entire block transfer is completed. u Problem –Conflicts accessing memory. Can either arbitrate access or get a more expensive dual ported memory system.

CIS3601 CIS 360: Introduction to Computer Systems Course Notes Wayne Heym Rick Parent

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