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1/1/ / faculty of Electrical Engineering eindhoven university of technology Introduction Part 2: Data types and addressing modes dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Data type basics High level data types must be mapped onto bit patterns which can be manipulated by the CPU The representation must be such that hardware is kept as simple as possible –Basic data types are stored in one word or fixed number of words (2, 4, 8: powers of two!) –Complex data types are not handled as a unit, the parts are addressed and manipulated separately

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Data type determination Generally the instruction determines the data type, not the stored bit patterns themselves –Data type enforcing is done by high level compiler ! ‘Tagging’ data with data type is possible –Requires extra memory bits for each data word –Data read must be type checked and/or converted This requires complex hardware and execution time!

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1/1/ / faculty of Electrical Engineering eindhoven university of technology 'Ordinals’: non-negative whole- numbers Encoded by giving 'weights' to the bits in a word and adding the weights of the '1' bits together N-1N-2012Bit number 2 N-1 2020 21212 2 N-2 Weight 12864421 For N=8 –Value range is 0..(2 N -1) for N bit values, possibility of overflow and underflow ! –Standard operations: Add, Subtract, Multiply, Divide, Shift (= mul/div by 2 N )

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ’Integers’: generic whole-numbers Encoding generally done using 'two's complement' N-1N-2012Bit number –2 N-1 2020 21212 2 N-2 Weight –12864421 For N=8 –Value range is –(2 N–1 )..(2 N–1 – 1) for N bit values, possibility of overflow and underflow ! –Other encodings can be used for integers: ‘one’s complement’ or ‘sign and magnitude’ –Standard operations as ordinals (different shift right) Different check for overflow/underflow

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Boolean logic values: one bit ‘true’/’false’ AND, OR and XOR mostly done on whole words –Some processors can perform boolean operations on single bits in a word (using special instructions) Compilers may use whole words for a boolean –Use specific bit patterns to denote true/false OR –Use only one bit in the word and disregard the rest OR –Use rules like 'all 0 = false, anything else = true' Conditional jumps normally based on bit flags which indicate the last instruction’s result Zero, Positive/Negative, Carry/Borrow, Overflow....

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Characters’: encoded readable text Uses arbitrary bit pattern encoding: international standards like ‘ASCII’ needed –Truly international character sets require a large amount of separate characters (Japanese, Chinese !) Only few operations make sense on characters –Comparing for equality is always possible –Comparing for higher/lower only if order is defined (an alphabet!) and encoded in the bit patterns –’Block move' instructions handle character sequences

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Binary fixed point values: fractions Change the bit weights of ordinals or integers –Example with range –16..+15.875 in steps of 0.125 –The binary point can be placed arbitrarily –The minimum step size is fixed by this choice –Program must manage the position of the binary point, there is no hardware support ! 76 012Bit number 345 –168 0.12 5 0.250.5Weight 124 True ‘real’ values are impossible

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Floating point’: more precise For a fixed number of bits, relative precision can be kept constant by moving the binary point value = base exponent mantissa Base is a fixed number, normally taken as 2 Mantissa is the basic value represented by a binary fixed point notation For base 2, mantissa range is normally [0..1) or [0..2) Mantissa also encodes the sign of the complete value Exponent indicates by how much the mantissa is scaled to smaller (exp. 0) values

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1/1/ / faculty of Electrical Engineering eindhoven university of technology The IEEE 754-185 floating point standard Lots of choices, a standard was needed ! Base is taken 2 here Mantissa is given as sign-and-magnitude value Separate sign bit Magnitude as fixed point binary with range [0..2) Exponent is given as ordinal with fixed negative offset –Minimum and maximum exponent values are special cases for encoding zero, overflow etc.

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ExponentMantissaValue 'IEEE floating point' exponent values –Mantissa [0..1) only for minimum exponent –Mantissa [1..2) only for non-minimum exponent Leftmost bit of mantissa can be determined from exponent! [1..2)normal value minimum normal maximum +/– 0(two different zero notations !) 0 +/– 'infinity’(may be result of overflow) 1 (0..1)'denormalised’(close to zero, reduced precision) [1..2)illegal, not allowed [0..1)illegal, not allowed [0..1)illegal, not allowed (1..2)'Not a Number’(NaN- to report/propagate errors)

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1/1/ / faculty of Electrical Engineering eindhoven university of technology E M minimum exponent maximum exponent exponent offset MSB mantissa total width IEEE format name: ‘IEEE floating point’ standard formats sign bit exponent mantissa (magnitude) single extended 11 bits 32 bits –1022 +1023 unspecified stored 44 bits double extended 15 bits 64 bits –16382 +16383 unspecified stored 80 bits single 8 bits 23 bits –126 +127 –127 not stored 32 bits double 11 bits 52 bits –1022 +1023 –1023 not stored 64 bits

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘IEEE floating point’ requirements (1) Several rounding modes must be present –Round towards zero –Round towards negative infinity –Round towards positive infinity –Round 'towards nearest or even’ (balances errors) A number of functions must be present too –Arithmetic: standard add, subtract, multiply and divide, but also remainder, square root, round-to-integer –Floating point integer or decimal string –Compare operations (may return ‘not comparable’) for ‘interval arithmetic’

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1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘IEEE floating point’ requirements (2) Precision of calculations must be very high –Results must really be rounded values of absolute precision calculations ! Must be possible to round to lower precision if more than just single precision is provided –Needed to simulate low precision format calculations Calculation errors must be logged and/or trapped –Can use ‘NaN’ to propagate error to end of calculation

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1/1/ / faculty of Electrical Engineering eindhoven university of technology 120 121 122 123 132 133 address 110 111 112 113 address Addressing arrays and records (structs) Map them on sequence of memory words –Address the sub-parts separately ! A[3] (word 1) A[3] (word 2) A[4] (word 1) A[9] (word 1) A[4] (word 2) A[9] (word 2) A = array [3..9] of 'double-word' base address = base + (index – 3) scale (to get to word 1 of each 'double-word') address = base + (index – 3) scale (to get to word 1 of each 'double-word') R =record p: word; q: boolean; r: 'double- word’ end; R.p (word) R.q (boolean) R.r (word 1) R.r (word 2) base offset offset = 0 offset = 1 offset = 2 & 3 address = base + offset scale (=2)

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1/1/ / faculty of Electrical Engineering eindhoven university of technology High level language stack ‘frames’ The stack plays a major role in high-level languages –A 'base' (or 'frame' ) pointer ‘BP’ references parameters and variables stored on the stack procedure p1 var p: word; p := f1(3); end; procedure p1 var p: word; p := f1(3); end; BP (for p1) function f1(x: word): word; var y: word; begin y := 1; f1 := x + y; end; function f1(x: word): word; var y: word; begin y := 1; f1 := x + y; end; SP ret. addr. p1 p (word) BP p1 caller 114 115 110 111 113 address 116 112 117x (value 3) SP ret. addr. f1 SP BP for p1 SP,BP (for s1) y (word) SP BP (for s1) 1: Push parameter(s) 2: Call subroutine 3: Push base pointer BP 4: Load BP with SP 5: SP SP + size of variable(s) run subroutine (result register) 1: Load SP with BP BP (for s1), SP 2: pop BP from the stack SP BP (for p1) 3: return from subroutine SP 4: SP SP – size of parameter(s) SP 5: use result value (from register) p (value 4)

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Basic adressing modes Immediate ADD #15 The instruction includes the (constant!) data itself Register ADD r1 A register contains the actual data Absolute (or ‘Direct’) ADD [105] A directly specified (constant) address contains the data Indirect ADD [r2] A register contains the address of the data Indexed (or ’Based') ADD [r4 + 14] A register and a fixed offset are added to address the data

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Some addressing mode ‘extensions’ Automatic increment/decrement ADD [r1++] –A register addresses the data and is modified Register pointed to previous data item:pre-increment Register pointed to next data item:pre-decrement Register must point to next data item:post-increment Register must point to previous item:post-decrement –The added/subtracted offset depends upon the data size Scaled index ADD [r2*4+123] –A register value multiplied by a scale factor (power of 2) and fixed offset are added to address the data –Used to access arrays with a fixed base position

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Some really complex addressing modes Double indirect ADD [[r3]] –A register contains the address of the address of the data –Some processors allow 'multiple indirect addressing’ (with a flag bit indicating the last address) Scaled indexed based offset ADD [r1*8+r2+14] –Can access an array local variable inside a subroutine: r1 = array index, 8 = array entry size, r2 = base pointer, 14 = offset from the base pointer to start of the array

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1/1/ / faculty of Electrical Engineering eindhoven university of technology Final addressing mode remarks Stack (relative) addressing uses the SP or BP registers in one of these modes as 'base' register True RISC processors only know immediate, register and indirect addressing modes The 'set' data type is generally implemented as a bitmap, using word-wide logical operations Other high-level data structures are normally constructed in software ! Hardware implementation is difficult but may be very attractive for speed !

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