1. CMOS Analog Design Using All-Region MOSFET Modeling 1 Chapter 11 MOSFET parameter extraction for design

2. CMOS Analog Design Using All-Region MOSFET Modeling 2 For V DS /  t =1/2 and i f =3, we have I S  I D. For V DS /  t =1/2 and i f =3, more accurate values for g m /I D and I S are 0.53 times the peak value of g m /I D and 1.13 times the measured current, respectively. For V DS /  t <<1 we have i f  i r or Specific current and threshold voltage

3. CMOS Analog Design Using All-Region MOSFET Modeling 3 Transconductance-to-current ratio of a MOSFET vs. gate voltage for V DS  Φ t /2 and V S =0.

4. CMOS Analog Design Using All-Region MOSFET Modeling 4 Pinch-off voltage vs. gate voltage For i f =3, the pinch-off voltage is equal to the source voltage.

5. CMOS Analog Design Using All-Region MOSFET Modeling 5 Slope factor n=1/(dV P /dV G ) vs. gate voltage

6. CMOS Analog Design Using All-Region MOSFET Modeling 6 Plot of 1/(n-1) 2 vs. pinch-off voltage The slope and the y-intercept of the interpolation line give  =0.60 V 1/2 and 2  F =0.89 V

7. CMOS Analog Design Using All-Region MOSFET Modeling 7 Mobility - 1 with The dependence of the mobility on the transverse electric field is written as Problem: Determine the mobility variation for cases in which the depletion charge is much higher than the inversion charge density

8. CMOS Analog Design Using All-Region MOSFET Modeling 8 Mobility-2 ParameterVT0VT0 2F2F  Value0.552 V0.89 V0.60 V 1/2 8.8  A 0.75 V -1/2 + VSVS V S +  t /2 VGVG

9. CMOS Analog Design Using All-Region MOSFET Modeling 9 Comparison between experiment and the ACM model in a 0.35  m technology-1 Experiment and ACM model for a long-channel (L=3.2  m) NMOS transistor in a 0.35  m CMOS technology, with V S =0 and V DS = 13 mV. The maximum error for currents is around 30% for V G = 3.3 V

10. CMOS Analog Design Using All-Region MOSFET Modeling 10 Comparison between experiment and the ACM model in a 0.35  m technology-2 Plots of experimental and modeled transconductance-to-current ratio vs. drain current

11. CMOS Analog Design Using All-Region MOSFET Modeling 11 Comparison between experiment and the ACM model in a 0.35  m technology-3 Plot of the experimental and modeled current vs. gate voltage for a minimum-length NMOS transistor in a 0.35  m technology.

12. CMOS Analog Design Using All-Region MOSFET Modeling 12 The Early voltage -1

13. CMOS Analog Design Using All-Region MOSFET Modeling 13 The Early voltage -2 Experimental drain and source currents versus drain-to-source voltage for a minimum channel length NMOS transistor (L=0.4  m) in a 0.35  m CMOS technology.

14. CMOS Analog Design Using All-Region MOSFET Modeling 14 The Early voltage -3 Derivatives of the experimental drain and source currents with respect to the drain voltage versus drain-to-source voltage for a minimum channel length NMOS transistor (L=0.4  m) in a 0.35  m CMOS technology.

15. CMOS Analog Design Using All-Region MOSFET Modeling 15 The Early voltage -4 Experimental and modeled Early voltages vs. drain-to-source voltage for a minimum-length NMOS transistor (L=0.4  m) in a 0.35  m CMOS technology

16. CMOS Analog Design Using All-Region MOSFET Modeling 16 The Early voltage - 5 Experimental and modeled Early voltages vs. drain-to-source voltage for transistors M 1, M 2, M 4, and M 8, for which the nominal lengths are L min, 2·L min, 4·L min, 8·L min, respectively, where L min =0.4  m.

17. CMOS Analog Design Using All-Region MOSFET Modeling 17 The Early voltage - 6 Transistor  [mV/V] a [V/m 2 ] [V] M1M1 72.5 10 14 0.1 M2M2 0.82.5 10 14 0.1 M4M4 0.62.5 10 14 0.1 M8M8 0.452.5 10 14 0.1 Fitting parameters extracted for the Early voltage of NMOS transistors in a 0.35  m CMOS technology.