1. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 12 Metallization

2. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Overview of Multilevel Metallization Interlayer Dielectric Metal interconnect structure Diffused active region in silicon substrate Sub quarter micron CMOS cross section Via interconnect structure with tungsten plug Metal stack interconnect Local interconnect (tungsten) Initial metal contact Figure 12.1

3. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Traditional vs. Damascene Metallization Traditional Interconnect Flow Oxide Via-2 etch Tungsten deposition + CMP Metal-2 deposition + etch Cap ILD layer and CMP Dual Damascene Flow Cap ILD layer and CMP Nitride etch-stop layer (patterned and etched) Second ILD layer deposition and etch through two oxide layers Copper fill Copper CMP Figure 12.2

4. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Copper Metallization Photograph courtesy of Integrated Circuit Engineering Photo 12.1

5. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda 1.Conductivity 2.Adhesion 3.Deposition 4.Patterning/Planarization 5.Reliability 6.Corrosion 7.Stress Requirements for Successful Metal Material

6. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Silicon and Select Wafer Fab Metals (at 20 ° C) Table 12.1

7. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Metals and Metal Alloys used in Wafer Fab Aluminum Aluminum-copper alloys Copper Barrier metals Silicides Metal plugs

8. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Aluminum Interconnect Figure 12.3

9. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Ohmic Contact Structure Gate Barrier metal Ohmic contact Aluminum, tungsten, copper, and so on Source Drain Oxide Figure 12.4

10. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Junction Spiking Junction short Shallow junction Figure 12.5

11. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Hillock on a Metal Line due to Electromigration Hillocks short-circuit two metal lines Void in metal line Figure 12.6

12. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda The Benefits of Copper Interconnect 1.Reduction in resistivity –1.678  -cm vs. 2.65  -cm for Aluminum 2.Reduction in power consumption 3.Tighter packing density 4.Superior resistance to electromigration 5.Fewer process steps –20 to 30 % fewer steps with damascene technique

13. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Change in Interconnect Delay Compared to 0.25-  m Device Generation Table 12.2

14. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Comparison of Properties/Processes Between Al and Cu Table 12.3

15. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Three Major Challenges to Using Copper Interconnects in Semiconductor Products 1.Copper diffuses quickly into oxides and silicon. 2.Copper cannot be easily patterned using regular plasma etching techniques. 3.Copper oxidizes quickly in air at low temperatures (<200  C) and does not form a protective layer to stop further oxidation.

16. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Barrier Layer for Copper Interconnect Structure Barrier metal Copper Figure 12.7

17. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda The Essential Properties of Barrier Metal 1.Good diffusion barrier properties so that the diffusivity of the two interface materials (e.g., tungsten and silicon) is low at the sintering temperature (sintering refers to joining of the materials by thermal means). 2.High electrical conductivity with low ohmic contact resistance. 3.Good adhesion between the semiconductor and metal. 4.Resistance to electromigration. 5.Stability when thin and at high temperature. 6.Resistance to corrosion and oxidation.

18. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Ta for Copper Barrier Metal Copper Tantalum Figure 12.8

19. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Refractory Metal Silicide at a Silicon Contact Titanium/titanium- nitride barrier metal Tungsten metal Titanium silicide contact Silicon substrate Polysilicon gate Titanium silicide contact Oxide Source Drain Figure 12.9

20. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Some Properties of Select Silicides Table 12.4

21. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Polycide on Polysilicon Titanium polycide Titanium silicide Polysilicon gate Doped silicon Figure 12.10

22. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Anneal Phases of TiSi 2 Figure 12.11

23. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Chip Performance Issues Related to a Salicide Structure STI TiSi 2 STI S G D TiSi 2 Reduced sheet resistance Reduced gate to S/D resistance Reduced contact resistance Reduced diode leakage Figure 12.12

24. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Formation of Self-Aligned Metal Silicide (Salicide) 2. Titanium deposition Silicon substrate 1. Active silicon regions Field oxide Spacer oxide Polysilicon Active silicon region 3. Rapid thermal anneal treatment Titanium-silicon reaction regions 4. Titanium strip TiSi 2 formation Figure 12.13

25. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Tungsten Plug for Multilevel Metal Layers Early metallization technique 1. Thick oxide deposition 2. Oxide planarization 3. Contact etch through oxide 4. Barrier metal deposition 5. Tungsten deposition 6. Tungsten planarization 1. Contact etch through oxide 2. Aluminum deposition 3. Aluminum etch Tungsten plugs inside contact holes (vias) Oxide (dielectric) Aluminum contacts Oxide (dielectric) Current metallization technique Figure 12.14

26. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Metal Plugs in IC SiO2 Photograph courtesy of Integrated Circuit Engineering Photo 12.2

27. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Metal Deposition Systems Physical Vapor Deposition (PVD) Evaporation Sputtering Metal CVD Copper electroplating

28. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Simple Evaporator Roughing pump Hi-Vac valve Hi-Vac pump Process chamber (bell jar) Crucible Evaporating metal Wafer carrier Figure 12.15

29. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Some Advantages of Sputtering 1.Ability to deposit and maintain complex alloys. 2.Ability to deposit high-temperature and refractory metals. 3.Ability to deposit controlled, uniform films on large wafers (200 mm and larger). 4.Ability of multichamber cluster tools to clean the wafer surface for contamination and native oxides before depositing metal (referred to as in situ sputter etch).

30. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Simple Parallel Plate DC Diode Sputtering System Exhaust e- DC diode sputterer Substrate 1) Electric fields create Ar + ions. 2) High-energy Ar + ions collide with metal target. 3) Metallic atoms are dislodged from target. Anode (+) Cathode (-) Argon atoms Electric field Metal target Plasma 5) Metal deposits on substrate 6) Excess matter is removed from chamber by a vacuum pump. 4) Metal atoms migrate toward substrate. Gas delivery + + + + + Figure 12.16

31. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Dislodging Metal Atoms from Surface of Sputtering Target + 0 High-energy Ar + ion Sputtered metal atom Metal atoms Cathode (-) Rebounding argon ion recombines with free electron to form a neutral atom. Figure 12.17

32. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Factors that Affect Sputter Yield 1.Incident angle of the bombarding ions. 2.Composition and geometry of the target material. 3.Mass of bombarding ions. 4.Energy of the bombarding ions.

33. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Different Species Landing on Substrate Anode (+) Cathode (-) Electric field Metal target Photons from plasma glow Sputtered atoms Substrate High energy electrons Neutrals - Ions including impurities X-rays from target bombardment - Ions – e-e- e-e- Figure 12.18

34. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Three Types of Sputtering Systems RF (radio frequency) Magnetron IMP (ionized metal plasma)

35. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda RF Sputtering System Argon Gas flow controller Turbo pump RF generator Matching network Microcontroller operator interface Exhaust Chuck Electrode Target Substrate Blocking capacitor Roughing pump Pressure controller Gas panel Figure 12.19

36. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Magnetron Sputtering DC power supply Heated wafer chuck Magnet Argon inlet Vacuum Pump Target Cathode Figure 12.20

37. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Collimated Sputtering Cross section of via showing coverage of resulting sputtered film. Ar Target Collimator Collimated Sputtering System Figure 12.21

38. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Concept of Ionized Metal Plasma PVD Substrate Electrode Titanium target + + RF field High-energy Ar + ion Ti + ion Sputtered Ti atom e-e- e-e- e-e- e-e- Plasma DC supply RF generator DC field DC bias supply Induction coil Figure 12.22

39. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Metal CVD Tungsten CVD –Excellent step coverage and gap fill –High electromigration resistance Copper CVD –Excellent conformality

40. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Blanket Tungsten CVD with Ti/TiN Barrier Metal Ti 2. Collimated Ti deposition covers bottom of via Gap fill dielectric Aluminum Via PECVD SiO 2 1. Interlayer dielectric via etch 3. CVD TiN conformal deposition TiN 4. CVD tungsten deposition Tungste n via fill 5. Tungsten planarization Tungsten plug Figure 12.23

41. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda PVD Cluster Tool Photo 12.3 Photo Courtesy of Applied Materials, Inc.

42. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Copper Electroplating - Cathode + Copper anode Substrate Plating solution Inlet Outlet Copper ion Copper atom attached to wafer + + Figure 12.24

43. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Electroplating Tool Used with permission from Novellus Systems, Inc. Photo 12.4

44. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Traditional Aluminum Structure SiO2 Photograph courtesy of Integrated Circuit Engineering Photo 12.4

45. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.1 [55] Copper Metallization using Dual Damascene Process Step: SiO 2 deposition Description: ILD oxide deposition with PECVD to desired thickness for via There is no critical gap fill therefore PECVD is acceptable.. SiO 2 Table 12.5.1

46. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Process Step:SiN etch stop deposition Description: Thin (250 Å) SiN etch stop is deposited on ILD oxide. The SiN needs to be dense and pinhole- free; therefore HDPCVD is used. SiN Table 12.5.2 Copper Metallization using Dual Damascene Table 12.5.2

47. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.3 Copper Metallization using Dual Damascene Process Step:Via patterning and etch Description: Photolithography to pattern and dry etch via openings into SiN. Strip photoresist after completion of etch. SiN Table 12.5.3

48. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.4 Copper Metallization using Dual Damascene Process Step:Deposit remaining SiO 2 Description: PECVD oxide deposition for remaining ILD oxide. SiO 2 Table 12.5.4

49. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.5 Copper Metallization using Dual Damascene Process Step:Interconnect patterning Description:Photolithography to pattern SiO 2 trench with resist. Previously patterned via openings are located in trench. Photoresist Table 12.5.5

50. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.6 Copper Metallization using Dual Damascene Process Step:Etch trench for interconnect and hole for via Description:Dry etch trench in ILD oxide, stopping on the SiN layer. Etch continues to form via opening by passing through opening in SiN. Table 12.5.6

51. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.7 Copper Metallization using Dual Damascene Process Step:Deposit Barrier Metal Description:Deposit Ta or TaN diffusion layer with ionized PVD on bottom and sidewalls of trench and via. Barrier metal Table 12.5.7

52. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.8 Copper Metallization using Dual Damascene Process Step:Deposit Cu seed layer Description:Deposit continuous Cu seed layer with CVD. The layer must be uniform and free of pinholes Cu seed layer Table 12.5.8

53. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.9 Copper Metallization using Dual Damascene Process Step:Deposit Cu fill Description:Deposit Cu fill with electrochemical deposition (ECD). Fill both via opening and trench. Copper layer Table 12.5.9

54. © 2001 by Prentice HallSemiconductor Manufacturing Technology by Michael Quirk and Julian Serda Table 12.5.10 Copper Metallization using Dual Damascene Process Step:Remove excess Cu with Description:CMP remove excess Cu using chemical mechanical planarization (CMP).This planarizes the surface and prepares for next level. The resulting surface is a planar structure with metal inlays in the dielectric to form the circuitry. Copper Table 12.5.10