1. Lec 3bSystems Architecture1 Systems Architecture Lecture 3b: Review of Sequential Logic Circuits Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan

2. Lec 3bSystems Architecture2 Introduction Objective: To understand how data can be stored in a computer. –Sequential vs. Combinational Logic –Flip-flop –Timed flip-flop –Implementing computer memory –Review of the simple computer model References: Dewdney, The New Turing Omnibus (Ch. 38 and 48).

3. Lec 3bSystems Architecture3 Combinational vs. Sequential Circuits A combinational circuit is a logic circuit without any loops. The same outputs are always computed for the same inputs. A sequential circuit contains two-state memory elements which can remember the state over time. The outputs depend on both the inputs and the current state. The state changes over time which is marked off in discrete steps by pulses emanating from a clock. The pulses coordinate activity. The loops maintain the “memorized” state.

4. Lec 3bSystems Architecture4 Flip-Flop (SR-Latch) A sequential logic circuit with two states. The two states are (Q=0, Q’=1) and (Q=1,Q’=0) Provided the input (R = 0, S = 0) is not allowed, the flip-flop can only be in one of these two states. Q Q’ S R

5. Lec 3bSystems Architecture5 Flip-Flop States The state (Q=0,Q’=1) corresponds to storing a 0. The state (Q=1,Q’=0) corresponds to storing a 1. If S (set) is 1, then the state is set to 1. If R (reset) is 1, then the state is set to 0. If R & S are 1, the state does not change. Old Q R S Q’ Next Q 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 0 1 0 1 0 1 Q Q’ S R

6. Lec 3bSystems Architecture6 Flip-Flop States The transitions of the flip-flop are conveniently described in the following state transition diagram (finite state machine). The arcs are labeled by the RS inputs that cause the transition. In the diagram, state 0 is when Q = 0 and Q’ = 1, and state 1 is when Q = 1 and Q’ = 0. 10 10 01 11 01 10

7. Lec 3bSystems Architecture7 A Clocked Flip-Flop Q Q’ S R clock

8. Lec 3bSystems Architecture8 n-bit Register A state variable containing n bits Built from an array of n flip-flops State changes when load selected and the clock is high

9. Lec 3bSystems Architecture9 n-bit Register R Q S Q’ R Q S Q’ clock load X0X0 X1X1

10. Lec 3bSystems Architecture10 Memory Cell R Q S Q’ input read = 1/write = 0 select output

11. Lec 3bSystems Architecture11 Memory N = 2 k words each l bits Inputs –k address bits –l data-in bits (for write) –flag to select read /write Outputs –l data-out bits (for read) Built from N  l array of memory cells –input, output, flag, select Decoder used to decode address Memory Address Input Output R/W

12. Lec 3bSystems Architecture12 Memory

13. Lec 3bSystems Architecture13 MBR MAR AC ALU PC IR(C) IR(O) Memory MUX 0 1 2 3 MUX 0101 0101 01230123 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 0 q 9 q 8 q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x1x2x3x4x5x1x2x3x4x5 DecoderT s s s s LOAD LOAD AD READ/ WRITE INC CLEAR INC