1. ES 244: Digital Logic Design Chapter 3 Chapter 3: Karnaugh Maps Uchechukwu Ofoegbu Temple University

2. ES 244: Digital Logic Design Chapter 3Riddle Three people check into a hotel. They pay $30 to the manager and go to their room. The manager suddenly remembers that the room rate is $25 and gives $5 to the bellboy to return to the people. On the way to the room the bellboy reasons that $5 would be difficult to share among three people so he pockets $2 and gives $1 to each person. Now each person paid $10 and got back $1. So they paid $9 each, totalling $27. The bellboy has $2, totalling $29. Where is the missing $1?

3. ES 244: Digital Logic Design Chapter 3 If implemented correctly, they almost always produce a minimum solution. They are more straightforward that algebraic manipulations They generally produce SOPs, but POS can be generated from their complements if required. Introduction to Karnaugh Maps

4. ES 244: Digital Logic Design Chapter 3 Two-variable Karnaugh maps A B 01 0 1 A’B’AB’ A’BAB A B A’ B’ A B 01 0 1 m0m0m0m0 m2m2m2m2 m1m1m1m1 m3m3m3m3

5. ES 244: Digital Logic Design Chapter 3 Product terms corresponding to groups of two. Three-variable Karnaugh maps

6. ES 244: Digital Logic Design Chapter 3 Four-variable Karnaugh maps

7. ES 244: Digital Logic Design Chapter 3 An implicant of a function is a product term. From the point of view of the map, an implicant is a rectangle of 1, 2, 4, 8,... (any power of 2) 1’s. That rectangle may not include any 0’s. Example: f = A’B’C’D’+A’B’CD+A’BCD+AB’CD+ABC’D’+ABC’D+ABCD Implicants 11 AB CD 100 10 11 01 00011110 1 1 1 1

8. ES 244: Digital Logic Design Chapter 3Implicants The implicants of f are: Minterms (1 implicant) ABCD Groups of 2 ACD BCD ACD BCD ABC’ ABD Groups of 4 CD

9. ES 244: Digital Logic Design Chapter 3 Prime Implicant: o o an implicant that (from the point of view of the map) is not fully contained in any one other implicant. Essential Prime Implicant: o o a prime implicant that includes at least one 1 that is not included in any other prime implicant. Prime and Essential Prime Implicants 11 100 10 11 01 00011110 1 1 1 1 AB CD

10. ES 244: Digital Logic Design Chapter 3 Minimum SOP Expressions From Karnaugh Maps

11. ES 244: Digital Logic Design Chapter 3 1. 1.Find all essential prime implicants. Circle them on the map and mark the minterm(s) that make them essential with an asterisk (*). 2.Find enough other prime implicants to cover the function. Do this using two criteria: a.Choose a prime implicant that covers as many new 1’s (that is, those not already covered by a chosen prime implicant). b.Avoid leaving isolated uncovered 1’s. Minimum SOP Expressions From Karnaugh Maps The main idea is 1.To Have all ones covered 2.To Have as few terms as possible 3.To have several rectangles with more 1’s and few rectangles with less 1’s

12. ES 244: Digital Logic Design Chapter 3Example f = w’x’y’z’+w’xy’z’+ w’xy’z+ w’xyz+ wx’y’z’+ w’xyz+ wxy’z’+ wxyz 1 1 AB CD 100 10 11 01 00011110 1 1 1 1 1 * * * * f = y’z’+wyz+w’xz unnecessary

13. ES 244: Digital Logic Design Chapter 3 In Groups f = b + a' c

14. ES 244: Digital Logic Design Chapter 3 Prime implicant A rectangle of 1, 2, 4, 8,... 1’s or X ’s not included in any one larger rectangle. From the point of view of finding prime implicants, X ’s (don’t cares) are treated as 1’s. Essential prime implicant A prime implicant that covers at least one 1 not covered by any other prime implicant (as always). Don’t cares ( X ’s) do not make a prime implicant essential. Don’t Cares

15. ES 244: Digital Logic Design Chapter 3Example f = Σm(1,7,10,11,13) + Σd(5,8,15) 1 AB CD 1 00 10 11 01 00011110 1 1 x x x F = BD + ACD + ABC 1 Use don’t cares to get as many minterms in each tem as possible

16. ES 244: Digital Logic Design Chapter 3 For the following problem, find the minimum SOP expression within the options given h(a,b,c) = Σm(0,1,5) + d(3,4,6,7) In groups a) a)h = a'b' + c + a b) b)h = a + c + b’ c) c)h = c + b’ d) d)h = b’ e) e)h = c

17. ES 244: Digital Logic Design Chapter 3 Implementation of Two Functions

18. ES 244: Digital Logic Design Chapter 3Example F = A’B’C’+A’BC’+ABC’+ABC; G = A’B’C+A’BC+ABC’+ABC F = A’C’+AB AB C 1 0 1 00011110 11 1 AB C 1 0 1 00011110 1 1 1 G = A’C+AB

19. ES 244: Digital Logic Design Chapter 3 F = AB + ABC G = AB + BC F = AB + ABC G = AB + ABC Example

20. ES 244: Digital Logic Design Chapter 3 f = ab + bc g = ab + ac f = ab + abc g = ab + abc Example

21. ES 244: Digital Logic Design Chapter 3 F = AC + ACD + ABC G = AC + ACD + ABC Example

22. ES 244: Digital Logic Design Chapter 3Try

23. Many electronic systems automatically invert gates Easier to fabricate with electronic components Basic gates used in integrated circuits (IC) digital logic families. NAND gate universal gate Could be used to construct any logic gate NAND, NOR

24. ES 244: Digital Logic Design Chapter 3 NAND gates. Alternate symbol for NAND. Symbols for NOR gate.

25. ES 244: Digital Logic Design Chapter 3 NAND Gate Implementation When we have a circuit consisting of AND and OR gates such that 1.the output of the circuit comes from an OR, 2.the inputs to all OR gates come either from a system input or from the output of an AND, and 3.the inputs to all AND gates come either from a system input or from the output of an OR. All gates are replaced by NAND gates, and any input coming directly into an OR is complemented.

26. ES 244: Digital Logic Design Chapter 3Example Try: g = wx(y+z)+x’y

27. ES 244: Digital Logic Design Chapter 3 NOR Gate Implementation When we have a circuit consisting of AND and OR gates such that 1.the output of the circuit comes from an AND, 2.the inputs to all OR gates come either from a system input or from the output of an AND, and 3.the inputs to all AND gates come either from a system input or from the output of an OR. All gates are replaced by NOR gates, and any input coming directly into an AND is complemented.

28. ES 244: Digital Logic Design Chapter 3Example Try: g = (x+y’)(x’+y)(x’+z)

29. ES 244: Digital Logic Design Chapter 3 XOR and XNOR A xor B is 1 if a = 1 or b is 1 and 0 if both are 1 or 0; Develop a truth table for XOR

30. ES 244: Digital Logic Design Chapter 3 1-17 20 21 22 23 Homework