1. Unit 7 Multi-Level Gate Circuits Nand and Nor Gates Fundamentals of Logic Design Roth and Kinny

2. 7.1 Multi-Level Circuits The maximum number of gates cascaded in series between a circuit input and the output is referred to as the number of levels of gates. Assume that all variables and their complements are available—ignore inverters.

3. 7.1 (cont.) 1. AND-OR – circuit means a two-level circuit composed of level of AND gates followed by an OR gate at the output. 2—OR-AND –circuit means a two-level circuit composed of level of OR gates followed by an AND gate at the output. 3.—OR-AND-OR circuit –means a three-level circuit with a level of OR gates followed by a level of AND gates, followed by a level of OR gates. 4. Circuit of AND and OR gates –implies no particular ordering.

4. 7.1 The number of levels in an AND-OR circuit can usually be increased by factoring. The number of levels in an OR-AND circuit can usually be increased by multiplying out.

5. 7.1 (cont.) Things to consider –Cost is related to the number of levels. –Gate delays may limit the number of levels.

6. 7.1(cont.) Figure 7.1 (page 200) shows an expression for Z with four levels, six gates, and 13 inputs. By partially multiplying out, we get Figure 7.2 (page 201). Pages 201 – 203 show a complete design example—start with K-map; factor; find f’ using K-map; multiply out.

7. 7.2 NAND and NOR Gates NAND and NOR Gates are generally faster and use fewer components than AND and OR gates. See Figure 7-8 and Figure 7-9, page 204.

8. 7.2 (cont.) A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of this set of operations. If a single gate forms a functionally complete set by itself, then any switching function can be realized using only gates of that type—the NAND gate is an example.

9. 7.2(cont.) Figure 7-10 illustrates realizations of NOT, AND, and OR NOR gates are another example of a gate that can be used as an OR, AND, or OR gate.

10. 7.3 Design of Two-Level NAND and NOR Gate Circuits Letting F = (F’)’ and then applying De Morgan’s Laws allows the conversion of a two level circuit of ANDs and ORs into one with NANDs. See page 206 Figure 7-11 illustrates eight basic forms for two-level circuits.

11. 7.3 Cont. Procedure for designing a minimum two- level NAND-NAND circuit. –(1) Find a minimum SOP expression for F. –(2) Draw the corresponding two-level AND- OR circuit. –(3) Replace all gates with NAND gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals.

12. 7.3 (cont.) Procedure for designing a minimum two- level NOR-NOR circuit. –1. Find a minimum PoS expression for F. –2. Draw the corresponding two-level OR – AND circuit –3. Replace all gates with NOR gates. Leave the gate interconnection unchanged. If the output gate has any single literals in inputs, complement these literals.

13. 7.4 Design of Multi-Level NAND and NOR Gate Circuits. See Figure 7-13 –Multi-Level Circuit conversion.

14. 7.5 Circuit Conversion Using Alternative Gate Symbols Figure 7.14—Note “bubbles”

15. 7.6 Design of Two-Level, Multiple- Output Circuits. Some gates can be used for more than one output. See Example, page 214-215, Equations (7-24), figure 7-20, 7-21, 7-22.