1. FPGA Design Flow Based on Using Seven-Segment Displays,
ECE 448: Spring 2014
Lab 3
FPGA Design Flow Based on
Xilinx ISE and Isim.
Using Seven-Segment Displays,
Buttons, and Switches.

2. Agenda for today Part 1: Distribution and testing of FPGA boards
Part 2: Seven Segment Displays
Part 3: User Constraints File
Part 4: Buttons and Switches
Part 5: Introduction to FPGA Design Flow based on Xilinx ISE
Part 6: Introduction to Lab 3
Part 7: Class Exercise 2

3. Distribution and Testing
Part 1
Distribution and Testing
of FPGA Boards 3

4. Seven Segment Displays
Part 2
Seven Segment Displays 4

5. Seven Segment Displays5

6. 4-Digit Seven Segment Display

7. Patterns for Decimal Digits

8. Patterns for Hexadecimal Digits

9. Connection to FPGA Pins

10. Multiplexing Digits

11. Time-Multiplexed Seven Segment Display

12. SSD_DRIVER SEG(6..0) Counter UP q(k-1..k-2) Counter UP Counter UP
clk AN OC
Counter UP
rst
OC – One’s Complement

13. Size of the counter
1 ms ≤ 2k * TCLK ≤ 16 ms
fCLK = 100 MHz
k = ?

14. User Constraint File (UCF)
Part 3
User Constraint File (UCF) 14

15. User Constraint File (UCF)
File contains various constraints for Xilinx
Clock Period
Circuit Locations
Pin Locations
Every pin in the top-level unit needs to have a pin in the UCF

17. User Constraint File (UCF) - SSD
# Seven Segment Displays
NET "SEG<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33";
NET "SEG<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33";
NET "SEG<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33";
NET "SEG<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33";
NET "SEG<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33";
NET "SEG<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33";
NET "SEG<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33";
NET "AN<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33";
NET "AN<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33";
NET "AN<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33";
NET "AN<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33";

18. User Constraint File (UCF) - LEDs
NET "LED<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33";
NET "LED<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33";
NET "LED<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33";
NET "LED<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33";
NET "LED<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33";
NET "LED<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33";
NET "LED<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33";
NET "LED<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33";

19. User Constraint File (UCF) CLOCK
# Buttons
NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33";

20. Part 4 Switches and Buttons20

21. Buttons 21

22. Connection of Buttons to FPGA Pins

23. Debouncing Buttons key bounce, tBOUNCE key bounce, tBOUNCE
Bouncing period typically smaller than 10 ms

24. to Generate Short Pulses (1)
Using DEBOUNCE_RED
to Generate Short Pulses (1)
RED – Rising Edge Detector

25. to Generate Short Pulses (2)
Using DEBOUNCE_RED
to Generate Short Pulses (2)

26. User Constraint File (UCF) Buttons
NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS
NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU
NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL
NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND
NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR

27. Using Switches 8 SW
SW_SIG

28. User Constraint File (UCF) Switches
NET "SW<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33";
NET "SW<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33";
NET "SW<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33";
NET "SW<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33";
NET "SW<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33";
NET "SW<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33";
NET "SW<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33";
NET "SW<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33";

29. Part 5 Hands-on Session on FPGA Design Flow based on Xilinx ISE
and Xilinx ISim 29

30. Part 6
Introduction to Lab 3
Movie Ticket
Dispensing Machine 30

31. Stage 1: Choose a Movie Default BTNU (UP) BTNR BTNL (RIGHT) LEFT BTND
DOWN
BTNS (Enter)

32. Stage 2: Choose Ticket Quantity
Use UP and Down buttons to change the quantity
BTNS (Enter)
= 49.50

33. Stage 3: Entering Bills $1 UP Total Amount $10 LEFT $20 RIGHT $5 DOWN
Blink for 5 sec
Change

34. Part 7
Lab Exercise 34

35. 16-bit Binary Up-Down Counter
Fig 1. Block Diagram

36. SSD_DRIVER SEG(6..0) Counter UP q(k-1..k-2) Counter UP Counter UP
clk AN OC
Counter UP
rst
OC – One’s Complement