1. Reconfigurable Clock Distribution Circuitry Circuit and Systems,2007.ISCAS 2007.IEEE International Symposium on 27-30 May 2007 Page(s):877 - 880 Atanu Chattopadhyay, Zeljko Zilic Department of Electrical and Computer Engineering, McGill University Montreal, Quebec, Canada Presented by: Ishrath Fatima

2. Features Skew ranges from 3.9-5.5ps for a 3-clock domain/15-tap configuration. Worst case skew under 4% for all frequencies. Power consumption of about 62.82mW No de-skewing method used. Frequency : 1.9GHz Clock Period: 525ps Reference-based scheme for skew compensation. Daisy chaining the clock to distribute clock without distortion and reducing the clock load. PLL replaced by delay lines, which reduces power consumption. Reconfigurable & reprogrammable clock distribution network.

3. Reference Based clock distribution

4. Reference Based clock distribution Architecture

5. Reference Based clock distribution scheme Device is sub-divided into multiple regions. H-Tree to distribute clock from tap to leaves. Bi-directional clock distribution line. Its scalable and compatible with irregularly shaped distribution areas. Clock distribution line has a constant delay ‘K’ over its entire length. Phases : Synchronization, Calibration and operation. Synchronization: The forward clock is delayed to align with reverse clock, which results in each local clock to a position directly between forward and reverse moving reference clocks, results in skew free clocks at each tap. Calibration: Disable source delay element for an appropriate “average clock”and align polarity of local clock’s by inverting appropriate taps. Operation: Unused circuitry disabled to save power. Each local delay line is required to save the delay settings determined during synchronization. Clock buffers allow us to re-direct clocks dynamically at certain pre- defined switch points, making distribution reconfigurable.

6. 15-tap Reconfigurable Clock Distributions

7. References A. Chattopadhyay and Z. Zilic “Reference-based clock distribution architectures,” Proc. MWSCAS 2006. H. Lee, H. Q. Nguyen, and D. W. Potter, “Design self-synchronized clock distribution networks in an SoC ASIC using DLL with remote clock feedback,” Proc ASICSOC 2000, 248-252

8. Questions??