1. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Timers

2. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Lecture Outline The Timer Sub-system Includes these Distinct Features: 16-bit Counter Seven-Stage Programmable Prescaling Eight Input Capture Channels Eight Output Compare Channels 16-bit Pulse Accumulator

3. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Look at Page 31 in Reference Manual for Actual Register Addresses Central element:16-bit free running counter –At reset counter is disabled –Once enabled, counter starts from $0000 and counts up continuously –When $FFFF is reached, counter rolls over to $0000 –Cannot be written to during operation (only writable in test mode) –May be reset upon successful Output Compare 7 General Description of Main Timer Bit 15 - Bit 8 Bit 7Bit 0 TCNT $0045 $0044 ----- ------

4. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Enabling the Free-Running Counter Timer Enable (TEN) bit determines operation of the timer and counter Writing a 1 to TEN turns on the counter, writing a 0 disables the system, reducing power consumption TEN TSWAI0 TSCR1$0046 TSFRZ TFFCA000 01234567

5. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Counter Prescaler Allows 8 clocking rates of the timer counter –E-Clock rate divided by: 1, 2, 4, 8, 16, 32, 64, 128 At reset the default prescale factor is 1 Prescale may be changed at any time Will take effect after some number of clock cycles where all prescale counter stages equal zero. (see p. 450 of Family Reference Manual for details)

6. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Changing the Counter Prescaler Trade-off between timer resolution and timer range TOI0 PR0 TSCR2 $004D 0 0TCRE PR2PR1 01234567 Prescale Factor Resolution (one count) Range (Overflow) PR2PR1PR0 1 2 4 8 16 32 64 128 125 ns 250 ns 500 ns 1  s 2  s 4  s 8  s 16  s 8.192 ms 16.38 ms 32.77 ms 65.54 ms 131.1 ms 262.1 ms 524.3 ms 1.049 s 0000111100001111 0011001100110011 0101010101010101

7. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Counter Overflows Timer overflow flag (TOF) status bit set each time the counter rolls over from $FFFF to $0000 TOF status bit can generate an automatic interrupt request by setting the timer overflow interrupt (TOI) enable bit TOF 00 TFLG2$004F 0 0000 01234567 TOI 0PR0 TSCR2$004D 0 0TCREPR2PR1 01234567

8. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Input Capture Vs. Output Compare Each of the eight I/O pins of Port T may be used as either an input capture or an output compare If IOSX is 0, the corresponding channel acts as an input capture If IOSX is 1, the corresponding channel acts as an output compare $0040TIOS

9. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Input Capture Concept Used to record the time an event occurs When an input signal is received, the time is stored in memory by capturing the contents of the free-running counter

10. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Features of Input Capture Function 16-bit registers Input edge-detection logic Interrupt generation logic

11. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Input Capture Registers Eight 16-bit input capture registers are available –Each register has a corresponding timer input pin (TC0- TC7) located on Port T pins PT0-PT7 When an edge is detected at a timer input pin, the current value of the free-running counter is stored in the corresponding input capture register

12. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Input Capture Registers (cont’d) Can be read at any time as a pair of 8-bit registers using instructions like LDD or LDX Writing to register when used as Input Capture has no meaning Bit 15 - Bit 8 Bit 7Bit 0 TC0 $0051 $0050 Bit 15Bit 8 Bit 7Bit 0 TC7 $005F $005E ----- ------ ------ ------ …

13. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Input Edge-Detection Logic Used to select which edge of an input is detected Configuration EDGxBEDGxA Capture Disabled00 Capture on Rising Edge Only01 Capture on Falling Edge Only10 Capture on Any Edge11 EDG0A TCTL4$004B 01234567 EDG0BEDG1AEDG1BEDG2AEDG2BEDG3AEDG3BEDG4A TCTL3$004A 01234567 EDG4BEDG5AEDG5BEDG6AEDG6BEDG7AEDG7B

14. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Interrupt Generation Logic Input capture status flags are automatically set to one each time a selected edge is detected Input capture interrupt enable bits If CXI is 1when CXF is set, interrupt condition is met C7FC6F C0F TFLG1$004E C5FC4FC3F C2FC1F 01234567 C7IC6I C0I TIE$004C C5IC4IC3I C2IC1I 01234567

15. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Application of Input Captures Period or frequency measurement – Capture the time of two successive rising or falling edges Pulse width measurement –Capture the time between two adjacent edges

16. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Short Period Measurement Code FIRSTEQU $2000DEFINE A 2-BYTE LOCATION TO STORE FIRST EDGE PERIODEQU $2002 DEFINE A 2-BYTE LOCATION TO STORE PERIOD ORG $1000 LDAA#$80 STAA$0046ENABLES FREE RUNNING COUNTER LDX#$0000 LDAA#$00ENSURES PT1 IS USED AS AN INPUT CAPTURE, TIOS STAA$0040NOTE: THIS IS THE CASE BY DEFAULT LDAA #$04 STAA $004BEDGE DETECTION FOR IC1 in TCTL4 SET TO RISING EDGES LDAA #$02 STAA $004ECLEARS ANY OLD FLAG FROM IC1F in TFLG1 LOOP1BRCLR$4E #$02LOOP1LOOP HERE UNTIL FIRST RISING EDGE IS DETECTED LDD $0052READ TIME OF FIRST CAPTURE in TC1 (Hi) STD FIRSTSTORE FIRST CAPTURE VALUE LDAA #$02 STAA $004ECLEAR THE IC1F FLAG BEFORE NEXT EDGE LOOP2BRCLR $4E #$02LOOP2LOOP HERE UNTIL NEXT RISING EDGE IS DETECTED LDD $0052READ TIME OF SECOND CAPTURE SUBD FIRSTFIND THE TIME DIFFERENCE BEWTEEN EDGES STD PERIODSTORE THE RESULT AS THE PERIOD (cycles) :

17. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Measuring Long Periods Using Counter Overflow Extending the range of the 16-bit counter with an 8-bit software counter –Software keeps track of counter overflows –Creates a 24-bit counter (16-bit + 8-bit) –Time values are stored as 3-byte numbers

18. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Application of Input Captures (cont’) Can be used as a time reference for an output function. –Input Capture records the event time –Offset representing time delay is added to the input capture and stored to an output compare. Both input captures and output compares are referenced from the same counter, so software latencies do not affect the accuracy to time delay

19. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Other Uses of Input Capture Pins Can be used as general purpose I/O pins when the timer functions are not needed Logic levels can be read even if the input- capture function is enabled Can serve as flexible interrupt input pins –Have some advantages over the IRQ pin

20. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare: Basic Concept 16 Bit Register Stores a Number …8 possible Registers to store this number: Comparator checks Number against Free Running Counter (TCNT Register) …Really 8 comparators-one for each channel …This is done in hardware, no processor time used When Counter matches TCx Register, it triggers an event

21. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 What “Event” is triggered? Three Non-Exclusive Possibilities: Changes the output of one or several of the pins in Port T Set a Flag in TFLG Register Cause an Interrupt

22. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare causes Port T Pins to change state (Part I) Output Compares 0 to 6: Each Output compare controls a SINGLE PIN: Output Compare 0PT0 Output Compare 1PT1 Output Compare 2PT2 Output Compare 3PT3 Output Compare 4PT4 Output Compare 5PT5 Output Compare 6PT6

23. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare causes Port T Pins to change state (Part II) Output Compares 0 to 6: TCTL1 ($0048) and TCTL2 ($0049) Registers Control How Each Pin Changes TCTL1 $1020

24. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare causes Port T Pins to change state (Part II)

25. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare causes Port T Pins to change state (Part III) Output Compare 7: Causes 8 Port T pins to change simultaneously Notice PT0-PT6 are also used by Output Compares 0-6 OC7M7OC7M6OC7M5OC7M4OC7M3OC7M2OC7M1OC7M0 Output Compare 7 Mask Register (OC7M) determines which Port T Pins will be Controlled by Successful Output Compare 7 PT7PT6PT5PT4PT3 OC7M $0042 OC7D $0043 OC7D7OC7D6OC7D5OC7D4OC7D3OC7D2OC7D1OC7D0 PT2PT1 PT0 OC7D Register sets value to be written to Port T pins selected in OC7M Register

26. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare Causes Flag to Be Set (Part I) When Output Compare is successful it sets corresponding Flag in TFLG1 Control Register: Software must constantly poll TFG1 register to check for flags C7FC6F C0F TFLG1$004E C5FC4FC3F C2FC1F 01234567

27. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare Causes Flag to be Set part (II) Use LDAA, STA commands to write 1 to Flag But DON’T USE BSET!!!! You Must clear the Flag after it is set You clear the Flag by writing a 1 to the corresponding Bit in TFLG1 Reg.

28. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Output Compare Causes an Interrupt Successful Output compare will cause an interrupt when corresponding bit in TIE Register is set: C7IC6I C0I TIE$004C C5IC4IC3I C2IC1I 01234567

29. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Measuring Long Intervals: Problems with Overflow Bit You must measure this length of time t time This is where timer rolls over (overflow) t Record Start Time Record End Time t=[T END -T START ]+(# of overflows)*(T overflow ) But I only have this much time to record last overflow …then I need to record the end time!

30. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Forced Output If you need to change state of Port T Pin BEFORE output compare occurs Use Forced Output…software triggers compare to occur and Pin T will change state accordingly FOC7FOC6FOC5FOC4FOC3 FOC2 FOC1FOC0 CFORC $0041

31. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Pulse Accumulator Overview Uses PT7 for inputs 16-bit Counter Incremented by: edge on pin IOC7 (PT7) logic level of pin IOC7 Used to: –Count number of events: Event Counting Mode –Measure duration of pulse: Gated Time Accumulation Mode

32. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Key Things to Know Can be read or written to at any time 2 Modes –Event Counter –Gated Time Accumulation Pulse Accumulator Input Pin: Port T Pin 7 Registers

33. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Pulse Accumulator Registers PACNT $0062 & $0063 –16 Bit PA Count PACTL $0060 PAFLG $0061 B15 B8 B7 B0

34. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Register Settings PAEN: 0 = Disabled, 1 = Enabled PAMOD: 0 = Event Counter, 1 = Gated Time MODEPAMODPEDGEPin Action Event Counter 00Falling Edge. This Edge detection sets PAIF 01Rising Edge. This edge detection sets PAIF Gated Time Accumulation 10Div. by 64 clock enabled with IOC7 input pin high. Trailing Falling edge on IOC7 sets PAIF flag 11Div. by 64 clock enabled with IOC7 input pin low. Trailing Rising edge on IOC7 sets PAIF flag.

35. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Register Settings CLK[0:1]: Timer Clock Selection PAOVF: 0 = No Overflow 1 = Overflow Flag Flag bit is cleared with a write to PAFLG register with bit 1 set PAOVI: 0 = Overflow interrupt inhibited 1 = Overflow Interrupt enabled PAIF: 0 = No input Edge Interrupt 1 = Input Edge Interrupt Flag Set when selected edge is detected at IOC7 input pin. Event edge triggers PAIF. Trailing edge of gated signal at IOC7 input pin triggers PAIF. PAI: 0 = Input edge interrupt inhibited 1 = Input edge interrupt enabled

36. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Event Counting Mode PAMOD = 0 Counts Active Edge of PAI pin Example: (PACNT = 0; PAEN = 1; PEDGE = 1: Rising Edge) PT7/ IOC7 16-BIT COUNTER PACNT PAI 1234 PACNT Value

37. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Event Counting Example A light emitter/detector pair can be used in an assembly line to count the number of parts going by.

38. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Gated Time Accumulation Mode PAMOD = 1 Free-running bus clock divided by 64 Subject to PT7/IOC7 pin being active PT7/ IOC7 Clock 16-BIT COUNTER PACNT bus/64 CLOCK (from Main Timer) AND

39. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Gated Time Example PACNT = 0; PAEN = 1; PEDGE = 1 –PEDGE = 1 (Trailing Rising Edge) (inhibit counting when PT7/IOC7 is 1) PT7 1234 PACNT Value bus/64 65

40. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Pulse Width Measurement Common use of Gated mode Measure duration of single pulses - period Easier than with Input Capture Counter is zero before pulse starts After pulse, pulse time directly read (need starting and ending count for input capture)

41. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Example: Interrupt at Specified Time Gated Time Accumulation (PAMOD = 1) Set Pulse Accumulator to interrupt after 5ms Steps: –Calculate time for one bus/64 cycle –Divide delay by time for one bus/64 cycle –Take 2’s complement and store in PACNT –When input goes to active level, counter will increment until overflow

42. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Assembly Code: Initialization to Count Negative Edges LDAA#$01 STAAPAFLG ;Clear PAIF by writing 1 to it LDAA#$41 ;PAEN = 1, PAMOD = 0, PEDGE = 0, PAI = 1 STAAPACTL

43. George W. Woodruff School of Mechanical Engineering, Georgia Tech ME4447/6405 Questions???