1. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 1 1 Chapter 5 Logic Built-In Self-Test

2. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 2 2 What is this chapter about?  Introduce the basic concepts of logic BIST  BIST Design Rules  Test pattern generation and output response analysis techniques  Fault Coverage Enhancement  Various BIST timing control diagrams  A Design Practice

3. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 3 3 Introduction  What are the problems in today’s semiconductor testing?  Traditional test techniques become quite expensive  No longer provide sufficiently high fault coverage  Why do we need built-in self-test (BIST)?  For mission-critical applications  Detect un-modeled faults  Provide remote diagnosis

4. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 4 4 BIST Techniques Categories  Online BIST  Concurrent online BIST  Non Concurrent online BIST  Offline BIST  Functional offline BIST  Structural offline BIST

5. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 5 5 A General Form of Logic BIST Non- concurrent BIST Offline Online Concurrent Functional Structural [Abramovici 1994] Logic BIST Techniques

6. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 6 6 ATypical Logic BIST System A Typical Logic BIST System Structural off-line BIST Logic BIST Controller Test Pattern Generator (TPG) Output Response Analyzer (ORA) Circuit Under Test (CUT)

7. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 7 7 BIST Design Rules Logic BIST requires much more stringent design restrictions when compared to conventional scan. Therefore, when designing a logic BIST system, it is essential that the circuit under test meet all scan design rules and BIST specific design rules, called BIST design rules.

8. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 8 8 Typical X-bounding Methods Methods for blocking an unknown (X) source

9. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 9 9 X-bounding Methods Depending on the nature of each unknown (X) source, several X-bounding methods can be appropriate for use. Common problems: (1) Increase the area of the design. (2) Impact timing.

10. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 10 10 Typical Unknown Sources  Analog Blocks  Adding bypass logic.  Adding control-only scan point  Memories and Non-Scan Storage Elements  Bypass logic  Initialization  Combinational Feedback Loops  Scan points

11. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 11 11 Typical Unknown Sources (cont’d)  Asynchronous Set/Reset Signals  using the existing scan enable (SE) signal to protect each shift operation and adding a set/reset clock point (SRCK) on each set/reset signal to test the set/reset circuitry. [Abdel-Hafez 2004]

12. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 12 12 Typical Unknown Sources (cont’d)  Asynchronous Set/Reset Signals Timing control diagram for testing data and set/reset faults

13. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 13 13 Typical Unknown Sources (cont’d)  Tri-State Buses  Re-synthesize each bus with multiplexers.  One-hot decoder A one-hot decoder for testing a tri-state bus with 2 drivers

14. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 14 14 Typical Unknown Sources (cont’d)  False Paths  0-control point  1-control point  Critical Paths  Adding an extra input pin to a selected combinational gate on the critical path.

15. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 15 15 Typical Unknown Sources (cont’d)  Multiple-Cycle Paths  0-control point  1-control point  Holding certain scan cell output states  Floating Ports  PI or PO must have a proper connection to Power (Vcc) or Ground (Vss).  Floating inputs to any internal modules must be avoided.

16. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 16 16 Typical Unknown Sources (cont’d)  Bi-directional I/O Ports  Fix the direction of each bi-directional I/O port to either input or output mode. Forcing a bi-directional port to output mode

17. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 17 17 Re-Timing Races and hazards caused by clock skews may occur between the TPG and the (scan chain) inputs of the CUT as well as between the (scan chain) outputs of the CUT and the ORA. To avoid these potential problems and ease physical implementation, we recommend adding re-timing logic between the TPG and the CUT and between the CUT and the ORA. D Q CK D Q O R A CK3 D Q CK D Q T P G CK1 CK2 CUT Re-timing logic among the TPG, CUT, and ORA

18. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 18 18 Test Pattern Generation  Test pattern generators (TPGs) constructed from linear feedback shift registers (LFSRs)  TPG  Exhaustive testing  Pseudo-random testing  Pseudo-exhaustive testing

19. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 19 19 Standard LFSR S i0 S i1 S in-2 S in-1 h n-1 h n-2 h2h2 h1h1  Consists of n D flip-flops and a selected number of exclusive-OR (XOR) gates An n-stage (external-XOR) standard LFSR [Golomb 1982]

20. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 20 20 Modular LFSR  Each XOR gate placed between two adjacent D flip-flops An n-stage (internal-XOR) modular LFSR [Golomb 1982] Si0 Si1 Sin-2 h1h1 h2h2 hn-2hn-1 Sin-1

21. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 21 21 LFSR Properties  The internal structure of the n-stage LFSR can be described by a characteristic polynomial of degree n, f(x). h i is either 1 or 0,depending on the feedback path

22. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 22 LFSR Properties 22

23. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 23 23 LFSR Properties  Let S i represent the contents of the n- stage LFSR after shifts of the initial contents,S 0,of the LFSR, and S i (x) be the polynomial representation of S i If T is the smallest positive integer such that f(x) divides,then the integer T is called the period of the LFSR.

24. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 24 LFSR Properties  If T = 2 n −1, then the n-stage LFSR generating the maximum-length sequence is called a maximum- length LFSR.  Define a primitive polynomial of degree n as a polynomial that divides 1+x T, but not 1+x i, for any integer i < T, where T = 2 n −1 [Colomb 1982]. 24

25. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 25 25 4-stage standard and modular LFSRs 4-stage Standard LFSR 4-stage Modular LFSR

26. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 26 4-stage standard and modular LFSRs  The first test sequence repeats after 6 patterns  The second test sequence repeats after 15 patterns, the LFSRs have periods of 6 and 15, respectively.  This further implies that 1+x^6 can be divided by 1+x^2 +x^4, and 1+x^15 can be divided by 1+x+x^4. 26

27. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 27 4-stage standard and modular LFSRs 27  A primitive polynomial is irreducible. Because T = 15 = 2 n −1,  the characteristic polynomial, f(x) = 1+x+x 4, used to construct the previous Figure is a primitive polynomial; thus, the modular LFSR is a maximum-length LFSR.

28. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 28 Finite field arithmetic  Arithmetic in a finite field is different from standard integer arithmetic. There are a limited number of elements in the finite field; all operations performed in the finite field result in an element within that field.finite fieldarithmetic 28

29. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 29 Finite field arithmetic  The finite field with p n elements is denoted GF(p n ) and is also called the Galois Field, in honor of the founder of finite field theory, Évariste Galois.Évariste Galois  A particular case is GF(2), where addition is exclusive OR (XOR) and multiplication is AND. Since the only invertible element is 1, division is the identity functionexclusive ORANDidentity function 29

30. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 30 Finite field arithmetic  For example, the following are equivalent representations of the same value in a characteristic 2 finite field:  Polynomial: x 6 + x 4 + x + 1  Binary: {01010011} 30

31. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 31 Finite field arithmetic  In a finite field with characteristic 2, addition modulo 2, subtraction modulo 2, and XOR are identical. Thus,  Polynomial: (x 6 + x 4 + x + 1) + (x 7 + x 6 + x 3 + x) = x 7 + x 4 + x 3 + 1  Binary: {01010011} + {11001010} = {10011001} 31

32. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 32 Finite field arithmetic  Under regular addition of polynomials, the sum would contain a term 2x 6, but that this term becomes 0x 6 and is dropped when the answer is reduced modulo 2.  Here is a table with both the normal algebraic sum and the characteristic 2 finite field sum of a few polynomials: 32

33. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 33 Finite field arithmetic (Multiplication)  (x 6 + x 4 + x + 1)(x 7 + x 6 + x 3 + x) = (x 13 + x 12 + x 9 + x 7 ) + (x 11 + x 10 + x 7 + x 5 ) + (x 8 + x 7 + x 4 + x 2 ) + (x 7 + x 6 + x 3 + x) = x 13 + x 12 + x 9 + x 11 + x 10 + x 5 + x 8 + x 4 + x 2 + x 6 + x 3 + x = x 13 + x 12 + x 11 + x 10 + x 9 + x 8 + x 6 + x 5 + x 4 + x 3 + x 2 + x 33

34. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 34 Example: LFSR  G(X) = X 3 + X 1 + 1 represents an LFSR with feedback taps 3 and 1 34

35. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 35 LFSR  For example, we may be asked to find all sets of maximal-length feedback taps for an LFSR with m=3 registers. We do this as follows: The length of the m-sequences will be N=2 3 - 1=7. We know that the solution lies in all the primitive factors of polynomial X 7 +1. We use modulo-2 linear algebra (probably with the aid of a computer algorithm) to find the prime factors to be 35

36. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 36 36 Hybrid LFSR Fully decomposable iff both b(x) and c(x) have no common terms and there exists an integer j such that Assume: f(x) is fully decomposable A (hybrid) top-bottom LFSR [Wang 1988a] can be constructed: Indicate the XOR gate with one input Is connected to the feedback path, not between stages

37. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 37 37 5-stage hybrid LFSRs (a) 5-stage top-bottom LFSR (b) 5-stage bottom-top LFSR

38. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 38 Hybrid LFSRs  Assume that a standard or modular LFSR uses m XOR gates, where m is an odd number.  If its characteristic polynomial, f(x), is fully decomposable, then a hybrid LFSR can be realized with only (m+1)/2 XOR gates. 38

39. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 39 39 Primitive polynomials list Primitive polynomials of degree n up to 100 Note: “24 4 3 1 0” means

40. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 40 40 Exhaustive Testing  Exhaustive Testing  Applying exhaustive patterns to an n-input combinational circuit under test (CUT)  Exhaustive pattern generator  Binary counter  Complete LFSR

41. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 41 41 Binary counter Example binary counter as EPG

42. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 42 42 Exhaustive Testing performance  Exhaustive Testing guarantees all detectable, combinational faults will be detected.  Test time maybe be prohibitively long if input number is larger than 20.

43. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 43 43 Pseudo-Random Testing  Pseudo-random pattern generator  Reduce test length but sacrifice the fault coverage  Difficult to determine the required test length and fault coverage

44. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 44 44 Pseudo-Random Testing  Maximum-length LFSR  RP-resistant problem  Weighted LFSR  Cellular Automata

45. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 45 45 Weighted LFSR Example weighted LFSR as PRPG

46. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 46 46 Cellular Automata  Provide more random test patterns  Provide high fault coverage in a random- pattern resistant (RP-resistant) circuit  Implementation advantage

47. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 47 47 Cellular Automata A general structure of an n-stage CA ‘0’ Cell 0 Cell 1 Cell n-2 Cell n-1 Each rule determines the next state of a cell based on the state of the cell and its neighbors

48. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 48 48 Cellular Automata

49. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 49 49 Example cellular automaton A 4-stage CA Test sequence X0X0 X1X1 ‘0’ X3X3 X2X2 0 0 0 1 0 0 1 0 0 1 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1 1 1 0

50. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 50 50 CA construction rules Construction rules for cellular automata of length n up to 53 [Hortensius 1989] * For n=7, Rule=152=001,101,010=1,101,010, where “0” denotes a rules 90 and “1” denotes a rule 150 cell, or vice versa

51. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 51 Cellular Automata Implementation 51 ‘0’ Cell 0 Cell 1 Cell n-2 Cell n-1

52. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 52 2-D Cellular Automata Implementation 52

53. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 53 2-D Cellular Automata Implementation 53

54. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 54 LFSR Implementation 54

55. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 55 55 Pseudo-Exhaustive Testing  Reduce test time while retaining many advantages of exhaustive testing  Guarantee 100% single-stuck fault coverage  Verification test technique [McCluskey 1984]  Segmentation test technique [McCluskey 1981]

56. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 56 56 Verification Testing Divide the CUT into m cones, backtracing from each output to determine the inputs that drive the output. Each cone will receive exhaustive test patterns and are tested concurrently. [McCluskey 1984] x1x1 y1y1 x2x2 y2y2 x3x3 y3y3 x4x4 y4y4 Pseudo-exhaustive pattern generators PEPGs

57. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 57 57 Syndrome Driver Counter Use SDC to generate test patterns. Check whether some inputs can share the same test signal. If n-p Inputs can share test inputs with other p inputs, then the circuit can be tested exhaustively with these p inputs. [Savir 1980] A 3-stage syndrome driver counter X1X1 X2X2 X3X3 X4X4

58. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 58 58 Constant-Weight Counter Use CWCs to generate test patterns. Constant-Weight counters are constructed using constant-weight code or M-out-of-N code. The constant-weight test set is a minimum-length test set for many circuits. [McCluskey 1982] A 3-stage constant-weight counter X1X1 X2X2 X3X3 X4X4

59. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 59 59 Combined LFSR/SR Use a combination of an LFSR and a shift register (SR) for pattern generation. The method is most effective when w is much less than n. In general, this technique requires much more tests than other schemes when w is greater than n/2. [Barzilai 1983 ] [Tang 1984] A 4-stage combined LFSR/SR X1X1 X2X2 X3X3 X4X4

60. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 60 60 Combined LFSR/PS A combined LFSR/PS approach using a combination of an LFSR and a linear phase shifter which includes a network of XOR gates to generate test pattern. Similar to combined LFSR/SR, this technique requires more tests than other schemes when w is greater than n/2. [Vasanthavada 1985] A 3-stage combined LFSR/PS X1X1 X2X2 X3X3 X4X4 X1X1 X2X2 X3X3

61. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 61 61 Condensed LFSR Condensed LFSRs are constructed based on linear codes. Define g(x) and p(x) as the generator polynomial and primitive polynomial over GF(2), respectively. An (n, k) condensed LFSR can be realized using Where [Wang 1986a]

62. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 62 62 Example Condensed LFSR A (4,3) condensed LFSR Test sequence X1X1 X2X2 X3X3 X4X4 1100 0110 0011 1010 0101 1001 1111 Set

63. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 63 63 Cyclic LFSR Use cyclic LFSRs to reduce the test length when w < n/2. A cyclic code always exists when  find a generator polynomial g(x) of largest degree k’ (or smallest degree k), for generating an (n’,k’) = (n’,n’-k) cyclic code, that divides 1+x^^n’ and has a design distance d > w+1;  construct an (n’,k) cyclic LFSR using f(x) = h(x)p(x) = (1+x^^n’)p(x)/g(x), where h(x) = (1+x^^n’)/g(x); and  shorten this (n’,k) cyclic LFSR to an (n,k) cyclic LFSR by deleting the rightmost, middle, or leftmost n’-n stages from the (n’,k) cyclic LFSR. To exhaustively test any (n,w) CUT

64. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 64 64 Example Cyclic LFSR A (8,5) cyclic LFSR, picking the first 6 stages and the last two stages of the (15,5) cyclic LFSR. An (n,k-s) shorted cyclic LFSR can be employed when 10100100 1010101 0 [Wang 1987b] [Wang 1988b]

65. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 65 65 Compatible LFSR (a) An (n,w) = (5,4) CUT (b) A 2-stage compatible LFSR The combined LFSR of an l-stage LFSR and an l-to-n mapping logic, called l-stage compatible LFSR, can further reduce the test length, when only single stuck faults are considered. Y1Y1 Y2Y2 X1X1 X2X2 X3X3 X4X4 X5X5 0 0 X1X1 X2X2 X3X3 X5X5 X4X4 Example compatible LFSR as PEPG

66. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 66 66 Segmentation Testing  Used when  Test length using previous techniques is too long or  Output depends on all inputs.  Divide the circuit into segments  Hardware partitioning  Sensitized partitioning

67. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 67 67 Delay Fault Testing  Need patterns to test delay fault exhaustively  Test set could cause test invalidation when more than one inputs change. TESTTYPE X1X1 X2X2 X n-1 XnXn h n-1 h n-2 h2h2 h1h1 0 1 [Bushnell 2000]

68. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 68 68 Output Response Analysis  Output response compacted to a signature  Then compared with golden signature  Compaction Techniques: Ones count testing Transition count testing Signature analysis

69. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 69 69 Ones Count Testing Assume the CUT has one output and the output contains a stream of L bits. Let the fault-free output response be Aliasing probability [Savir 1985] Ones count testing will need a counter to count the number of 1s in the bit stream. Example: R0 ={0101100}, OC=4, m= OCR = 3 and L = 7, POC(m )= 34/127 = 0.27

70. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 70 70 One Count Testing Signature CUT T Counter CLK One counter as ORA

71. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 71 71 Transition Count Testing Transition count testing is similar to that for ones count testing, except the signature is defined as the number of 1-to-0 and 0-to-1 transitions. Aliasing probability [Hayes 1976] In the previous example, where m= TCR0 = 4 and L = 7,P(TC(m)) = 29/127 = 0.23 R0 ={0101100}, OC=4,

72. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 72 72 Transition Count Testing Transition counter as ORA CUT T Signature Counter CLK D Q riri r i-1

73. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 73 73 Signature Analysis Signature analysis is the most popular compaction technique used today, based on cyclic redundancy checking. Two signature analysis schemes  Serial signature analysis  Parallel signature analysis

74. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 74 74 Serial Signature Analysis r0r0 r n-2 r n-1 h1h1 h2h2 h n-2 h n-1 M r1r1 An n-stage single-input signature register Define L-bit output sequence M Let the polynomial of the modular be f(x) IF Signature is the polynomial remainder, r(x)

75. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 75 75 Example M A 4-stage SISR

76. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 76 76 Example M A 4-stage SISR

77. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 77 SISR 77  fault detection or aliasing problem of an SISR  E or error polynomial E(x) of the fault-free sequence M and a faulty sequence M’.

78. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 78 SISR 78

79. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 79 79 Parallel Signature Analysis Multiple-input signature register (MISR) An n-input MISR can be remodeled as a single-input SISR with effective input sequence M(x) and effective error polynomial E(x) M1M1 M2M2 M0M0 M n-2 M n-1 h1h1 h2h2 h n-2 h n-1 r0r0 r1r1 r n-1 r n-2

80. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 80 80 4-stage MISR A 4-stage MISR M1M1 M2M2 M0M0 M3M3 M0M1M2M3M0M1M2M3 1 0 0 1 0 0 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 1 1 M An equivalent M sequence Aliasing probability

81. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 81 4-stage MISR 81

82. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 82 82 Logic BIST Architectures Four Types of BIST Architectures:  No special structure to the CUT  Make use of scan chains in the CUT  Configure the scan chains for test pattern generation and output response analysis  Use concurrent checking circuitry of the design

83. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 83 83 Type I - Centralized and Separate Board-Level BIST (CSBL) Two LFSRs and two multiplexers are added to the circuit. The first LFSR acts as a PRPG, the second serves as a SISR. The first multiplexer selects the inputs, another routes the PO to the SISR. [Benowitz 1975] CSBL Architecture n PIs CUT (C or S) MUX SISR k 1 m MUXMUX n 1 k = [log 2 m] PRPG n TEST POs

84. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 84 84 Type I - Built-In Evaluation and Self- Test (BEST) Use a PRPG and a MISR. Pseudo-random patterns are applied in parallel from the PRPG to the chip primary inputs (PIs) and a MISR is used to compact the chip output responses. [Perkins 1980] BEST Architecture POs CUT (C or S) MISRMISR PRPGPRPG PIs

85. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 85 85 Type II - LSSD On-Chip Self-Test (LOCST) In addition to the internal scan chain, an external scan chain comprising all primary inputs and primary outputs is required. The External scan-chain input is connected to the scan-out point of the internal scan chain. [Eichelberger 1983] LOCST Architecture S in CUT (C) S i S o POs PIs SRL R2R2 SISR PRPG S out SRL R1R1

86. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 86 86 Type II - Self-Testing Using MISR and Parallel SRSG (STUMPS) Contains a PRPG (SRSG) and a MISR. The scan chains are loaded in parallel from the PRPG. The system clocks are then pulsed and the test responses are scanned out to the MISR for compaction. New test patterns are scanned in at the same time when the test responses are being scanned out. [Bardell 1982]

87. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 87 87 STUMPS PRPG MISR CUT (C or S) CUT (C or S) Linear Phase Compactor MISR Linear Phase Shifter PRPG STUMPS A STUMPS-based Architecture

88. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 88 88 Type III - Built-In Logic Block Observer (BILBO) The architecture applies to circuits that can be partitioned into independent modules (logic blocks). Each module is assumed to have its own input and output registers (storage elements), or such registers are added to the circuit where necessary. The registers are redesigned so that for test purposes they act as PRPGs or MISRs. [Konemann 1980]

89. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 89 89 Built-In Logic Block Observer Scan-In X0X0 0 1 DQ B1B1 B2B2 Y0Y0 Y2Y2 Y1Y1 DQ DQ SCK X1X1 Scan-Out/X 2 A 3-stage BILBO

90. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 90 90 Type III - Concurrent Built-In Logic Block Observer (CBILBO) A 3-stage concurrent BILBO (CBILBO) [Wang 1986c]

91. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 91 91 Type III - Circular Self-Test Path (CSTP) All primary inputs and primary outputs are reconfigured as external scan cells. They are connected to the internal scan cells to form a circular path. During self-test, all primary inputs (PIs) are connected as a shift register (SR), whereas all internal scan cells and primary outputs (POs) are reconfigured as a MISR. [Krasniewsk 1989]

92. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 92 92 Circular Self-Test Path (a) The CSTP architecture (b) Self-Test cell CUT (C) PIs S in 0 1 CIRCULATE S out MISR SR POs TEST 0 1 X i-1 YiYi XiXi DQ CLK CSTP architecture

93. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 93 93 Type IV - Concurrent Self-Verification (CSV) CSV Architecture Checking Circuitry Functional CircuitryDuplicate Circuitry mm two-rail checker PRPG n

94. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 94 94 Summary Representative Logic BIST Architectures B: board-level testing C: combinational circuit S: sequential circuit

95. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 95 95 Fault Coverage Enhancement Three approaches to enhance the fault coverage  Test point insertion  Mixed-mode BIST  Hybrid BIST

96. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 96 96 Test Point Insertion Two typical types of test points

97. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 97 97 Test Point Insertion Example An example where one control point and one observation point are inserted to increase the detection probability of a 6-input AND-gate.

98. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 98 98 Test Point Placement  Fault simulation guided techniques  Testability measure guided techniques  Timing-driven test point insertion techniques Where to place the test points in the circuit to maximize the coverage and minimize the number of test points required.

99. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 99 99 Control Point Activation  Random activation  Deterministic activation During normal operation, all control points must be deactivated. During testing, there are different strategies as to when and how the control points are activated.

100. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 100 100 Mixed-Mode BIST Mixed-mode BIST is an alternative way to improve fault coverage without modifying the CUT. Pseudo-random patterns are generated to detect the RP- testable faults, and then some additional deterministic patterns are generated to detect the RP-resistant faults.

101. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 101 101 Mixed-Mode BIST  ROM Compression.  LFSR Reseeding.  Embedding Deterministic Patterns. Approaches for generating deterministic patterns on-chip: … … … … … LFSR Seeds Poly. Id Decoding Logic ….. Reseeding with multiple- polynomial LFSR Bit-flipping BIST

102. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 102 102 Hybrid BIST For manufacturing fault coverage enhancement where a tester is present, deterministic data from the tester can be used to improve the fault coverage.  Top-up ATPG  Store the compressed deterministic patterns on the tester

103. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 103 103 BIST Timing Control  To test Multiple-clock-domain circuits  To detect Intra-clock-domain faults and inter-clock-domain faults  Capture-clocking schemes  Single-capture  Skewed-load  Double-capture

104. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 104 104 One-Hot Single-Capture A capture pulse is applied to one clock domain, while holding all other test clocks inactive, during each capture window. Benefit: a single and slow global scan mode signal Drawback: long test time CK1 CK2 GSE Shift Window Capture Window … C1 Shift Window C2 … Capture Window … Shift Window … …… d1d1 d2d2 One-hot single-capture

105. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 105 105 Staggered Single-Capture Benefits: short test time; a single and slow global scan mode signal Drawback: some structural fault coverage loss CK1 CK2 Shift WindowCapture Window Shift Window … … … … C1 C2 GSE d2d2d3d3d1d1 Staggered single-capture

106. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 106 106 Skewed-Load  An at-speed delay test technique  Address intra-clock-domain delay faults  Three approaches  One-hot skewed-load  Aligned skewed-load  Staggered skewed-load

107. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 107 107 One-Hot Skewed-Load Tests all clock domains one by one by applying a-shift-followed by-a-capture pulses to detect intra-clock-domain delay faults. Drawbacks: (1) Cannot detect inter-clock-domain delay faults (2) Test time is long (3) Single and global scan enable (GSE) signal can no longer be used

108. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 108 108 Aligned Skewed-Load  Solve the long test time problem  Test all intra-clock-domain and inter- clock-domain faults  Need complex timing-control

109. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 109 109 Aligned Skewed-Load S3 CK1 CK2 CK3 SE1 SE2 SE3 S2 S1 C Capture aligned skewed-load Launch aligned skewed-load

110. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 110 110 Staggered Skewed-Load When two test clocks cannot be aligned precisely, we can simply insert a proper delay to eliminate the clock skew. The two last shift pulses are used to create transitions and their output responses are caught by the next two capture. Drawback: Need at-speed scan enable signal for each clock domain CK1 SE1 Shift Window Capture Window Shift Window …… S1C1 d1d1 d3d3 CK2 SE2 … C2 … S2 d2d2 Staggered skewed-load

111. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 111 111 Double Capture  Solve the physical implementation difficulty using skewed-load  True at-speed test  Double-capture benefit s  Detect intra-clock-domain faults and inter-clock-domain structural faults or delay faults at-speed  Facilitate physical implementation  Ease integration with ATPG

112. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 112 112 One-Hot Double-Capture Test all clock domains one by one by applying two consecutive capture pulses at their respective domains’ frequencies to test intra-clock-domain delay faults. Benefit: true at-speed testing of intra-clock-domain delay faults Drawbacks: (1) Cannot detect inter-clock-domain delay faults (2) Test time is long One-Hot double-capture

113. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 113 113 Aligned Double-Capture Aligned double-capture - I Aligned double-capture - II C3 CK1 CK2 CK3 C2 C1 C GSE C CK1 CK2 CK3 Capture Window C1 C4 C2 GSE C3

114. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 114 114 Staggered Double-Capture In the capture window, two capture pulses are generated for each clock domain. The first two capture pulses are used to create transitions at the outputs of scan cells, and the output responses to the transitions are caught by the next two capture pulses, respectively. Staggered double-capture Shift Window Capture WindowShift Window … … … … CK1 CK2 C1C2 C3C4 GSE d2d2d3d3d4d4d1d1d5d5

115. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 115 115 Fault Detection  Intra-clock-domain delay fault detection is relatively easy.  Testing inter-clock-domain delay faults is more complex.  A single capture yields the highest fault coverage of inter-clock-domain delay faults. GSE CK1 CK2 Shift WindowCapture WindowShift Window … … … … C1 C2 d

116. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 116 116 Fault Detection Capability Note: A hybrid double-capture scheme using staggered double-capture and aligned double-capture seems to be the preferred scheme for true at-speed testing

117. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 117 117 A Design Practice An example of designing a logic BIST system for testing a scan-based design (core) comprising two clock domains using s38417 and s38584. The two clock domains are taken from the ISCAS-1989 benchmark circuits [Brglez 1989]. Design statistics

118. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 118 118 Design flow  BIST Rule Checking and Violation Repair  Logic BIST System Design  RTL BIST Synthesis  Design Verification and Fault Coverage Enhancement

119. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 119 119 BIST Rule Checking and Violation Repair  The number of test clocks present in the design  The number of set/reset clocks present in the design All DFT rule violations of the scan design rules and BIST-specific design rules must be repaired. In addition, we should be aware of the following design parameters:

120. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 120 120 Logic BIST System Design  The type of logic BIST architecture to adopt  The number of PRPG-MISR (or PEPG-MISR) pairs to use  The length of each PRPG-MISR (or PEPG-MISR) pair  The faults to be tested and BIST timing control diagrams to be used  The types of optional logic to be added The second step is to design the logic BIST system at the RTL, including:

121. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 121 121 Logic BIST Architecture A logic BIST system for testing a design with 2 cores We choose to implement a STUMPS-based architecture, since it is easy to integrate with scan/ATPG and is the industry widely used architecture.

122. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 122 122 TPG and ORA Next, we need to determine the length of each PRPG-MISR pair. Using a separate PRPG-MISR pair for each clock domain allows us to reduce the Length of each PRPG and MISR. PRPG-MISR Choices

123. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 123 123 Test Controller The test controller plays a central role in coordinating the overall BIST operation. Often, external signals are controlled through an IEEE 1149.1 Boundary-Scan Standard based test access port (TAP) controller.

124. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 124 124 Test Controller (cont) In order to test structural faults in the BIST-ready core, we choose the Staggered single-capture approach. Slow-speed timing control using staggered single-capture

125. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 125 125 Test Controller (cont) In order to test delay faults in the BIST-ready core, we choose the Staggered double-capture approach if CD1 and CD2 are asynchronous, or the aligned double-capture approach if they are synchronous. Staggered double-capture Aligned double-capture

126. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 126 126 Clock Gating Block In order to generate an ordered sequence of single-capture or double-capture clocks, clock suppression [Rajski 2003] [Wang 2004], daisy-chain clock-triggering, or token-ring clock-enabling [Wang 2005a] can be used. Daisy-chain clock-triggering

127. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 127 127 Clock Gating Block (cont) A daisy-chain clock-triggering circuit A clock suppression circuit

128. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 128 128 Re-Timing Logic we recommend adding two pipelining registers between each PRPG and the BIST-ready core, and two additional pipelining registers between the BIST-ready core and each MISR. In this case, the maximum scan chain length for each clock domain,CD1 or CD2, is effectively increased by 2, not 4.

129. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 129 129 Fault Coverage Enhancing Logic and Diagnostic Logic In order to improve the circuit’s fault coverage, we recommend adding extra test points and additional logic for top-up ATPG support at the RTL. We also recommend including diagnostic logic in the RTL BIST code to facilitate debug and diagnosis. Example test modes to be supported by the logic BIST system

130. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 130 130 RTL BIST Synthesis At this stage, it is possible to either design the logic BIST system by hand or generate the RTL code automatically using a (commercially available) RTL logic BIST tool. In either case, the number of scan chains for each clock domain should be specified along with the names of their associated scan inputs (SIs) and scan outputs (SOs) without inserting the actual scan chains into the circuit.

131. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 131 131 Design Verification and Fault Coverage Enhancement Finally, the synthesized netlist needs to be verified with functional and/or Timing verification. Next, fault simulation needs to be performed on the pseudo-random Patterns generated by the TPG in order to determine the circuit’s fault coverage. Fault simulation and test point insertion flow

132. EE141 VLSI Test Principles and Architectures Ch. 5 - Logic BIST - P. 132 132 Concluding Remarks  STUMPS is an industry widely adopted logic BIST architecture, but hits problems due to low fault coverage.  Some challenges ahead  Whether the CBILBO-based architecture proposed by Wang and McCluskey would perform as it always guarantee 100% single stuck-fault coverage.  Whether pseudo-exhaustive testing would become the preferred BIST technique.