1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Selected Topics in VLSI Design Results of Phase 2: Final FPGA Design by Christoph Niemann and Vincent Wiese 30.10.2013 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Content Observations Multiplier Reworked Filter Coefficients Architecture Changes Carry-Save Adder General Architecture Improvements Metric + FIR-Result Future Improvements

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Observations Direct Form I has long critical path  Direct Form II much better filter is close to symmetric  unnecessary multipliers unnecessary length of filter coefficients CSD Recoding for filter coefficients can lead to customized multiplier per stage Ripple-Carry Adder is fastest CPA on FPGA (even faster than CLA Adder) pipelining can cut critical path

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Multiplier - Reworked Filter Coefficients use of 8-Bit coefficients instead of 16-Bit halves the theoretical number of partial products CSD-Recoding leads to an average number of n/3 non-zeroes in the coefficients (max. (n+1)/2) and even less for our two-complements result: 1-3 non-zeroes per filter coefficient  1-3 partial products to be summed

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Multiplier – Architecture Changes Inspired by: Timmermann (2008): Script „Algorithmen der Datentechnik“ Old Design: Inspired by: Timmermann (2008): Script „Algorithmen der Datentechnik“ A= O (coeff_width‘ * data_width) T= O (coeff_width‘) coeff_width‘ = # of non-zeroes in coeff_width redundant Carry-Save Adders instead of CPAs no Wallace Tree necessary for 3 partial products output: two vectors (Carry-Save representation) individuel design for each multiplier New Design Example:

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Carry Save Adder redundant adder with 3 input and 2 output vectors Inspired by: Timmermann (2008): Script „Algorithmen der Datentechnik“ A= O(data_width) T= O(1)

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 General Architecture Improvements Direct Form II implemented reduced number of multipliers due to filter symmetry only CS-Adders between stages  doubled registers for CS-Representation one CPA to determine final output  3 pipeline stages to cut it‘s critical path further individuel customizations for all used components Inspired by: Timmermann (2008): Script „Algorithmen der Datentechnik“

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Metric SynthesisedBackannotatedOld Metric Maximum Frequency:504,796 MHz554,016 MHz 53,378 MHz # of Slice Registers:328328 762 # of Slice LUTs:355355 5321 Metric: 1104,70 [MHz³]1460,38 [MHz³] 0.038 MHz 3  10 times as fast as before  by using less then half of the registers and not even 7% of the LUT‘s  metric increased by factor 3,8*10 4

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 FIR Result

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 10 Future Improvements a better style of coding for easier maintenance and further development removel of unnecessary components additional pipeline-stages depending on the metric changes due to the change of platform

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 11 Thank you for your attention!